Adjustable lock-in circuit for phase-locked loops

• US 7,242,254 B2
• Filed: 04/08/2005
• Issued: 07/10/2007
• Est. Priority Date: 04/08/2005
• Status: Expired due to Fees

• Current Assignee: Smart Semiconductor, LLC (Equitable IP Corporation)
• Original Assignee: ANA Semiconductor
• Inventors: Park, Sangbeom
• Primary Examiner(s): Pascal, Robert
• Assistant Examiner(s): Gannon, Levi
• Application Number:
  US11/102,021
• Publication Number:
  US 20060226915A1
• Time in Patent Office: 823 Days
• Field of Search: 331/17, 331/57, 331/DIG.2, 331/16
• US Class Current: 331/16
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/101 using an additional control signal to the controlled loop oscillator derived from a signal generated in the loop H03L7/113, H03L7/187 take precedence
• CPC Class Codes: Y10S 331/02 Phase locked loop having lock indicating or detecting means

Abstract

The adjustable lock-in circuits basically include a sensor, a reference voltage, two stacked PMOS transistors, two stacked NMOS transistors, and a feedback line. The sensor compares a feedback voltage with a reference voltage. If the sensing voltage does not reach the reference voltage, the output voltage of the sensor turns on the corresponding transistor, which provides a current to its output until the voltage at feedback reaches the reference voltage. The time to reach the expected voltage level is simply equal to the charge stored at the filter divided by the current, which can be scaled by a device aspect ratio of the transistor. Consequently, all adjustable lock-in circuits provide an adjustable initial loop condition closer to the expected loop condition according to a targeted lock-in time. In addition, the initial loop condition is varied by changing the reference voltage level.

Claims

1. An adjustable lock-in circuit for enabling any phase-locked loop to become locked according to a targeted lock-in time, comprising:

a feedback line connected with the output of the adjustable lock-in circuit and also coupled to the output of a filter;

a sensor for comparing a feedback voltage with a reference voltage and providing its output;

two stacked PMOS transistors connected between power supply and the output; and

two stacked NMOS transistors connected between the output and ground.

2. The circuit as recited in claim 1 wherein the sensor is a lower-voltage sensing comparator.

3. The circuit as recited in claim 2 wherein the lower-voltage sensing comparator'"'"'s output is coupled to the gate terminal of the upper PMOS transistor.

4. The circuit as recited in claim 1 wherein the sensor is a high-voltage sensing comparator.

5. The circuit as recited in claim 4 wherein the high-voltage sensing comparator'"'"'s output is coupled to the gate terminal of the lower NMOS transistor.

6. The circuit as recited in claim 1 wherein the sensors are both a low-voltage sensing comparator and a high-voltage sensing comparator.

7. The circuit as recited in claim 6 wherein the low-voltage sensing comparator'"'"'s output is coupled to the gate terminal of the upper PMOS transistor and the high-voltage sensing comparator'"'"'s output is coupled to the gate terminal of the lower NMOS transistor.

8. The circuit as recited in claim 1 wherein the sensor is operational amplifier.

9. The circuit as recited in claim 1 wherein the sensor is an amplifier with a reference voltage.

10. The circuit as recited in claim 1 wherein the sensor is a comparator with a reference voltage.

11. The circuit as recited in claim 1 further comprising a power-down NMOS transistor so that no current flows into the circuit during power-down mode.

12. The circuit as recited in claim 11 wherein the output of the adjustable lock-in circuit is coupled to a filter connected between the output and ground.

13. The circuit as recited in claim 11 wherein the output of the adjustable lock-in circuit is at ground during power-down mode.

14. The circuit as recited in claim 1 further comprising a power-down PMOS transistor and a power-down inverter so that no current flows into the circuit during power-down mode.

15. The circuit as recited in claim 14 wherein the output of the adjustable lock-in circuit is coupled to a filter connected between the output and power supply.

16. The circuit as recited in claim 14 wherein the output of the adjustable lock-in circuit is at power supply during power-down mode.

17. The circuit as recited in claim 1 wherein the reference voltage is output of any digital-to-analog converter whose digital data inputs are programmed.

18. The circuit as recited in claim 1 wherein the reference voltage is based on selecting tap of a segmented resistor string by a digital circuit that is coupled to the segmented resistor string.

19. The circuit as recited in claim 1 wherein the adjustable lock-in circuit is applied to all phase-locked loops without regard to architectures, topologies, and schematics.