Dual processor framer

• US 7,245,725 B1
• Filed: 05/17/2002
• Issued: 07/17/2007
• Est. Priority Date: 05/17/2001
• Status: Active Grant

• Current Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Beard, Paul
• Primary Examiner(s): Zand, Kambiz
• Assistant Examiner(s): Simitoski, Michael J.
• Application Number:
  US10/147,765
• Time in Patent Office: 1,887 Days
• Field of Search: 375/295, 380/261, 380/270, 713/323, 713/300, 455/68
• US Class Current: 380/270
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3293 by switching to a less power-consuming processor, e.g. sub-CPU
• CPC Class Codes: H04L 2209/80 Wireless network architectures or network communication protocols for wireless network security H04W12/00
• CPC Class Codes: H04L 9/00 Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A dual processor framer includes a receiver and a transmitter which share common circuitry and/or code. Separate direct memory access controllers may be used for each of the receiver and transmitter. Processing is distributed over two or more processors. One processor may be a lower power processor while another processor may be a higher power processor. At least one of the two or more processors may be programmable or reconfigurable. The transceiver is configured to provide internal loop back self testing at various points in the processing. Timing within the transceiver may be established almost entirely by a single clock domain.

Claims

1. A device including a transceiver, said device comprising:

a framer engine to encrypt and encode data to be transmitted through a wireless medium and to decode and decrypt data that is received through the wireless medium;

a first processor for controlling operations of the framer engine;

a power amplifier that changes between a plurality of operating power levels; and

a second processor for sending notifications to the power amplifier to change the operating power levels;

wherein the first processor is adapted to communicate using a first type of data words that includes fewer bits of data than a second type of data words communicated by the second processor.

2. A device including a transceiver, said device comprising:

a framer engine to encrypt and encode data to be transmitted through a wireless medium and to decode and decrypt data that is received through the wireless medium;

a first processor for controlling operations of the framer engine;

a power amplifier that changes between a plurality of operating power levels; and

a second processor for sending notifications to the power amplifier to change the operating power levels;

wherein the first processor is adapted to communicate using a first type of data words that includes a different amount of bits of data than a second type of data words communicated by the second processor.

3. The device of claim 2 wherein the first type of data words each comprise 16 bits of data and the second type of data words each comprise 64 bits.

4. The device of claim 2 wherein the first processor is integrally formed with the device while the second processor is detachably coupled to the device.

5. The device of claim 2 wherein the second processor is adapted to issue instructions causing the transceiver to power down for sleep mode.

6. The device of claim 2 further comprising logic encoded in one or more tangible media for execution and when executed operable to test operation of the transceiver and the framer engine by transmitting encoded wireless communications from a transmit portion of the transceiver directly to a receiver portion of the transceiver for decoding, said transmission from the transmitter portion directly to the receiver portion occurring independently of any other transceivers and independently of any remote wireless devices.

7. The device of claim 2 wherein the first processor is configured to operate at a first selectable operating power mode selected from a plurality of different selectable operating power modes and the second processor constantly operates at a second fixed power mode.

8. The device of claim 2 wherein the second processor is configured to operate at a first selectable operating power mode selected from a plurality of different selectable operating power modes and the first processor constantly operates at a second fixed power mode.

9. The device of claim 2 wherein one of the processors is configured to operate at a first selectable operating power mode selected from a plurality of different selectable power operating modes and a remaining one of the processors is configured to constantly operate at a second fixed power mode.

10. The device of claim 2 wherein the first type of data words communicated by the first processor include more bits of data than the second type of data words communicated by the second processor.

11. An apparatus comprising:

means for framing, encrypting and encoding data to be transmitted through a wireless medium and decoding and decrypting data that is received through the wireless medium;

means for controlling the framing, encrypting and encoding and decrypting and decoding using one or more first processors;

means for changing between a plurality of operating power levels of a power amplifier; and

means for sending notifications to the power amplifier that control the changes between operating power levels using one or more second processors;

wherein the first processors are adapted to communicate using a first type of data words that includes a different amount of bits of data than a second type of data words communicated by the second processors.

12. The apparatus of claim 11 wherein one of the two types of data words contains 32 bits of data and the remaining type of data words contains 8 bits of data.

13. The apparatus of claim 11 wherein one of the two types of data words contains 64 bits of data and the remaining type of data words contains 16 bits of data.

14. The apparatus of claim 11 wherein the one of the two types of data words contains four times as many bits as the remaining type of data words.

15. The apparatus of claim 11 further comprising testing the apparatus by transmitting encoded wireless communications from a transmit portion of the apparatus directly to a receiver portion of the apparatus for decoding, said transmission from the transmitter portion directly to the receiver portion occurring independently of any other transceivers and independently of any remote wireless devices.

16. The apparatus of claim 11 wherein one of the first and second processors are configured to operate at a first selectable operating power mode selected from a plurality of different selectable power operating modes and a remaining one of the first and second processors are configured to constantly operate at a second fixed power mode.

17. The apparatus of claim 11 wherein the first processors are integrally formed with the device while the second processors are detachably coupled to the device.