Active-pixel image sensors

• US 7,253,837 B2
• Filed: 04/04/2003
• Issued: 08/07/2007
• Est. Priority Date: 04/05/2002
• Status: Active Grant

• Current Assignee: STMicroelectronics Limited (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Limited (STMicroelectronics NV)
• Inventors: Henderson, Robert, Hurwitz, Jonathan Ephriam David
• Primary Examiner(s): Ometz; David
• Assistant Examiner(s): NEGRON, WANDA M
• Application Number:
  US10/407,871
• Publication Number:
  US 20040027470A1
• Time in Patent Office: 1,586 Days
• Field of Search: 348/241, 348/243, 348/300, 348/216.1, 250/208.1
• US Class Current: 348/241
• CPC Class Codes: H04N 25/616 involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
• CPC Class Codes: H04N 25/672 between adjacent sensors or output registers for reading a single image

Abstract

An image sensor has an array of pixels read by column circuits to provide reset and read samples on a pair of sample capacitors. To alleviate the effects of parasitic capacitance in the region of the sample capacitors, a modified timing arrangement is used. Both sample switches are operated simultaneously to pre-charge both sample capacitors with a pixel signal value. One sample switch is operated after reset to apply a reset value to one of the pre-charged sample capacitors.

Claims

1. A method of operating an image sensor comprising an array of active pixel elements, each column of pixels having an output circuit including a pair of sample capacitors and associated switches for applying pixel voltages to the sample capacitors, the method comprising:

operating the switches to apply a readout value to both sample capacitors;

applying a reset voltage for changing a state of the pixel;

operating the switches to apply a reset value to one of the capacitors; and

utilizing a difference of resulting voltages on the capacitors as the image value for the pixel.

2. The method of claim 1, wherein each pixel comprises a three-transistor pixel.

3. The method of claim 1, wherein each pixel comprises a pinned-photodiode pixel.

4. The method of claim 1, wherein operating the switches to apply the readout value to both sample capacitors is performed at the end of a time interval from release of the pixel from a preceding reset, the time interval being selected to define a desired exposure period.

5. A method of operating an image sensor comprising an array of active pixels and output circuits each including a pair of sample capacitors, the method comprising:

applying a readout value to both sample capacitors;

applying a reset voltage for changing a state of the pixel;

applying a reset value to one of the capacitors; and

generating an image value for the pixel by differencing resulting voltages on the sample capacitors.

6. The method of claim 5, wherein each pixel comprises a three-transistor pixel.

7. The method of claim 5, wherein each pixel comprises a pinned-photodiode pixel.

8. The method of claim 5, wherein applying the readout value to both sample capacitors is performed at the end of a time interval from release of the pixel from a preceding reset, the time interval being selected to define a desired exposure period.

9. An image sensor comprising:

an array of active three transistor pixels, each column of three transistor pixels including a column output line and an output circuit comprising a pair of sample capacitors and a respective pair of switches connecting the sample capacitors to the column output line; and

timing means for operating the switches to apply a readout value to both sample capacitors, to apply a reset voltage which changes the state of the three transistor pixel, and to operate one of the switches to apply a reset value to one of the sample capacitors.

10. The image sensor according to claim 9, wherein the image sensor is a solid state CMOS image sensor.

11. An image sensor comprising:

an array of active three transistor pixels, each column of three transistor pixels including a column output line and an output circuit comprising a pair of sample capacitors selectively connected to the column output line; and

a timing circuit to apply a readout value to both sample capacitors, to apply a reset voltage which changes the state of the three transistor pixel, and to apply a reset value to one of the sample capacitors.

12. The image sensor according to claim 11, wherein the image sensor is a solid state CMOS image sensor.

13. A method of operating an image sensor comprising an array of pixels and output circuits each including a pair of sample capacitors, the method comprising:

applying a reset value to both sample capacitors;

changing a state of the pixel by at least applying a transfer gate voltage to the pixel;

applying a readout value to one of the capacitors, and

generating an image value for the pixel by differencing resulting voltages on the sample capacitors.

14. The method of claim 13, wherein each pixel comprises a three-transistor pixel.

15. The method of claim 13, wherein each pixel comprises a pinned-photodiode pixel.

16. An image sensor comprising:

an array of four transistor pinned photodiode pixels having a transfer gate, each column of four transistor pinned photodiode pixels including a column output line and an output circuit comprising a pair of sample capacitors selectively connected to the column output line; and

a timing circuit to apply a reset value to both sample capacitors, to apply a transfer voltage to the transfer gate which changes a state of the four transistor pinned photodiode pixel, and to apply a readout value to one of the sample capacitors.

17. The image sensor according to claim 16, wherein the image sensor is a solid state CMOS image sensor.