Method and apparatus for generating a phase locked spread spectrum clock signal

• US 7,254,157 B1
• Filed: 03/27/2002
• Issued: 08/07/2007
• Est. Priority Date: 03/27/2002
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Crotty, Patrick J., Lesea, Austin H.
• Primary Examiner(s): PHU, PHUONG M
• Application Number:
  US10/109,130
• Time in Patent Office: 1,959 Days
• Field of Search: 375/130, 375/132, 375/135, 375/376, 375/373, 331/57, 331/177, 331/177.R
• US Class Current: 375/132
• CPC Class Codes: H03K 3/84 Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators

Abstract

A method of and apparatus for generating a spread spectrum clock signal on an integrated circuit are provided. A target frequency generated by a ring oscillator can be modulated by varying a supply voltage to the ring oscillator, thereby changing the target frequency. In one embodiment, the supply voltage is generated by an analog multiplexer that can be digitally controlled. A fixed voltage source can provide an input signal to the analog multiplexer. In one embodiment, the fixed voltage source can be implemented with a unity gain amplifier.

Claims

1. A spread spectrum clock generator, comprising:

a fixed voltage source for providing a first voltage;

an analog multiplexer including a chain of serially-connected resistors of a voltage divider, a plurality of transistors, and a controller adapted to selectively turn on and off each of the transistors for each of a plurality of time periods, wherein the chain of serially-connected resistors of the voltage divider is coupled between the first voltage from the fixed voltage source and a second voltage, and each of the transistors selectively couples a respective node that is between two of the serially-connected resisters in the chain of the voltage divider, to an output of the analog multiplexer;

a ring oscillator including a plurality of inverters that have a voltage supply coupled to the output of the analog multiplexer;

a buffer that couples the output of the analog multiplexer to the voltage supply of the inverters of the ring oscillator, wherein the buffer comprises a unity gain amplifier; and

a range shifter that includes another chain of serially-connected resistors of the voltage divider, another plurality of transistors, and another controller adapted to selectively turn on each of the another plurality of transistors, wherein the another chain of serially-connected resistors is coupled between the second voltage of the analog multiplexer and ground, and each of the another plurality of transistors selectively couples to the ground a respective node, which is between two of the serially-connected resisters in the another chain of the voltage divider.

2. The spread spectrum clock generator of claim 1, wherein turning on a predetermined set of the transistors by the controller of the analog multiplexer provides a predetermined output voltage at the output of the analog multiplexer.

3. The spread spectrum clock generator of claim 2, wherein the plurality of transistors have a thick gate oxide.

4. The spread spectrum clock generator of claim 1, wherein the controller of the analog multiplexer uses a pseudo-random pattern from a linear feedback shift register to selectively turn on and off each of the plurality of transistors of the analog multiplexer for each of the time periods.

5. The spread spectrum clock generator of claim 4, wherein the ring oscillator further includes a plurality of multiplexers for selectively bypassing a delay of a respective subset of the inverters of the ring oscillator, a delay of the inverters that are not bypassed providing a target frequency of the ring oscillator.

6. The spread spectrum clock generator of claim 5, wherein the first voltage is a fixed voltage of 1.5 volts.

7. An integrated circuit, comprising:

a plurality of integrated circuit elements; and

a spread spectrum clock generator generating a clock signal for controlling the Plurality of integrated circuit elements, the spread spectrum clock generator comprising;

a fixed voltage source for providing a first voltage;

an analog multiplexer including a chain of serially-connected resistors of a voltage divider, a plurality of transistors, and a controller adapted to selectively turn on and off each of the transistors for each of a Plurality of time periods, wherein the chain of serially-connected resistors of the voltage divider is coupled between the first voltage from the fixed voltage source and a second voltage, and each of the transistors selectively couples a respective node, which is between two of the serially-connected resisters in the chain of the voltage divider, to an output of the analog multiplexer; and

a ring oscillator including a plurality of inverters that have a voltage supply coupled to the output of the analog multiplexer,

wherein the controller of the analog multiplexer of the spread spectrum clock generator uses a pseudo-random pattern from a linear feedback shift register to selectively turn on and off each of the transistors of the analog multiplexer for each of the time periods, and

wherein the spread spectrum clock generator further comprises a range shifter that includes another chain of serially-connected resistors of the voltage divider, a plurality of transistors, and a controller adapted to selectively turn on each of the transistors, wherein the another chain of serially-connected resistors is coupled between the second voltage of the analog multiplexer and ground, and each of the transistors selectively couples to the ground a respective node, which is between two of the serially-connected resisters in the another chain of the voltage divider.

8. The integrated circuit of claim 7, wherein the ring oscillator of the spread spectrum clock generator further includes a plurality of multiplexers for selectively bypassing a delay of a respective subset of the inverters of the ring oscillator, a delay of the inverters that are not bypassed providing a target frequency of the clock signal.

9. The integrated circuit of claim 8, wherein the integrated circuit comprises a programmable logic device (PLD).