Wafer-level package and methods of fabricating

• US 7,256,069 B2
• Filed: 04/09/2001
• Issued: 08/14/2007
• Est. Priority Date: 06/28/1999
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Wood, Alan G., Akram, Salman
• Primary Examiner(s): Graybill; David E.
• Application Number:
  US09/832,160
• Publication Number:
  US 20010021541A1
• Time in Patent Office: 2,318 Days
• Field of Search: 438/125, 438/106, 438/108, 438/127, 438611-617, 438/667, 438/680, 438/681, 438/761, 438/763, 438/780, 438/977, 438/FOR.363, 438/FOR.485, 438/FOR.495, 257/758, 257/759, 257/760, 257/698, 257/736
• US Class Current: 438/108
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/06136 Covering only the central area of the surface to be connected, i.e. central arrangements
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01075 Rhenium [Re]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/12044 OLED

Abstract

A carrier for use in a chip-scale package, including a polymeric film with apertures defined therethrough. The apertures, which are alignable with corresponding bond pads of a semiconductor device, each include a quantity of conductive material extending substantially through the length thereof. The carrier may also include laterally extending conductive traces in contact with or otherwise in electrical communication with the conductive material in the apertures of the carrier. Contacts may be disposed on a backside surface of the carrier. The contacts may communicate with the conductive material disposed in the apertures of the carrier. A conductive bump, such as a solder bump, may be disposed adjacent each or any of the contacts. A chip-scale package including the carrier of the present invention is also within the scope of the present invention. Such a chip-scale package includes a semiconductor device invertedly disposed over the carrier such that bond pads of the semiconductor device substantially align with apertures formed through the carrier. Thus, the bond pads of the semiconductor device may communicate with the conductive bumps by means of the conductive material disposed in the apertures of the carrier. Methods of fabricating the carrier of the present invention and methods of fabricating chip-scale packages including the carrier are also within the scope of the present invention.

Claims

1. A method for fabricating a chip-scale package, comprising:

positioning a preformed polymeric film including at least one aperture that extends substantially longitudinally therethrough over a semiconductor device with the at least one aperture in substantial alignment with a corresponding bond pad of the semiconductor device; and

introducing conductive material in an at least partially liquid state into the at least one aperture.

2. The method of claim 1, further comprising adhering the preformed polymeric film to the semiconductor device.

3. The method of claim 1, further comprising defining at least another aperture through the preformed polymeric film.

4. The method of claim 3, wherein defining is effected after positioning.

5. The method of claim 3, wherein defining is effected before positioning.

6. The method of claim 1, wherein introducing comprises bonding the conductive material to the corresponding bond pad.

7. The method of claim 1, further comprising depositing conductive material onto the preformed polymeric film and within the at least one aperture.

8. The method of claim 7, wherein depositing comprises chemical vapor depositing or physical vapor depositing the conductive material.

9. The method of claim 1, wherein introducing comprises placing a preformed conductive structure within the at least one aperture.

10. The method of claim 1, further comprising forming at least one contact at an end of the conductive material, opposite the semiconductor device.

11. The method of claim 10, further comprising placing a conductive structure adjacent the at least one contact.

12. The method of claim 11, wherein placing comprises applying solder to the at least one contact.

13. The method of claim 1, further comprising positioning at least one conductive trace on the preformed polymeric film and in communication with the conductive material.

14. The method of claim 13, further comprising forming at least one contact in communication with the conductive trace.

15. The method of claim 14, further comprising placing a conductive structure adjacent the at least one contact.

16. The method of claim 15, wherein placing comprises applying solder to the at least one contact.

17. The method of claim 1, further comprising placing the preformed polymeric film on at least a portion of a peripheral edge of the semiconductor device.

18. The method of claim 15, further comprising placing polymeric material at least laterally adjacent the conductive structure.

19. The method of claim 15, further comprising placing a conductive elastomer over at least one conductive structure.

20. The method of claim 19, further comprising placing another conductive structure in contact with the conductive elastomer, opposite the at least one conductive structure.