Resistance-reduced semiconductor device and methods for fabricating the same

• US 7,256,498 B2
• Filed: 07/28/2005
• Issued: 08/14/2007
• Est. Priority Date: 03/23/2004
• Status: Expired due to Fees

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Hsu, Ju-Wang, Shieh, Jyu-Horng, Huang, Yi-Chun
• Primary Examiner(s): Pert; Evan
• Assistant Examiner(s): MANDALA, VICTOR A
• Application Number:
  US11/190,913
• Publication Number:
  US 20050258499A1
• Time in Patent Office: 747 Days
• Field of Search: None
• US Class Current: 257/758
• CPC Class Codes: H01L 21/28052 the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer formed by metal ion implantation H01L21/28044
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 29/06 characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Abstract

Semiconductor devices and methods for fabricating the same. The semiconductor device includes a resistance-reduced transistor with metallized bilayer overlying source/drain regions and gate electrode thereof. A first dielectric layer with a conductive contact overlies the resistance-reduced transistor. A second dielectric layer having a first conductive feature overlies the first dielectric layer. A third dielectric layer with a second conductive feature overlies the second dielectric layer, forming a conductive pathway down to the top surface of the metallized bilayer over one of the source/drain regions or the gate electrode layer.

Claims

1. A resistance-reduced semiconductor device, comprising:

a resistance-reduced transistor, comprising;

a gate stack on a silicon-containing substrate;

a pair of source/drain regions in the silicon-containing substrate, oppositely adjacent to the gate stack;

a metallized bilayer overlying each source/drain region to thereby reduce a resistance thereof, wherein the metallized bilayer comprises a metal top layer;

a first dielectric layer having a conductive contact, overlying the resistance-reduced transistor;

a second dielectric layer having a first conductive feature, overlying the first dielectric layer, wherein the first conductive feature and the conductive contact electrically form a conductive pathway down to the top metal layer over one of the source/drain regions;

a third dielectric layer having a second conductive feature, overlying the second dielectric layer; and

a first conductive cap layer partially overlying the first conductive feature, wherein the first conductive cap layer exposes a portion of the top surface of the first conductive feature to thereby contact the second conductive feature directly and the first conductive feature.

2. The semiconductor device as claimed in claim 1, further comprising a metal silicide layer disposed between the metal top layer and each source/drain region.

3. The semiconductor device as claimed in claim 2, wherein the metal top layer comprises the same type of metal ion as that of the metal silicide layer.

4. The semiconductor device as claimed in claim 1, wherein the metal top layer comprises refractory metal.

5. The semiconductor device as claimed in claim 2, wherein the metal silicide layer comprises a silicide of a refractory metal.

6. The semiconductor device as claimed in claim 1, further comprising a second conductive cap layer overlying a top surface of the first conductive features.

7. The semiconductor device as claimed in claim 6, wherein the second conductive cap layer comprises a metal or a metal-containing material.

8. The semiconductor device as claimed in claim 1, wherein the first conductive cap layer comprises a metal or a metal-containing material.