Saving power when in or transitioning to a static mode of a processor

  • US 7,260,731 B1
  • Filed: 10/23/2000
  • Issued: 08/21/2007
  • Est. Priority Date: 10/23/2000
  • Status: Expired due to Term
First Claim
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1. A method for reducing power utilized by a processor comprising the steps of:

  • determining that a processor is transitioning from a computing mode to a mode in which a system clock to the processor is disabled, andreducing core voltage to the processor to a value sufficient to maintain state during the mode in which said system clock is disabled, wherein said value of the core voltage is not sufficient to maintain processing activity in said processor,responsive to said determining, at a voltage regulator supplying said core voltage, transitioning from a first regulation mode to a second regulation mode,wherein power is dissipated during a voltage transition that reduces said selectable voltage in said first regulation mode and power is saved during said voltage transition in said second regulation mode.

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