Thin-film transistor with vertical channel region

• US 7,265,393 B2
• Filed: 10/28/2005
• Issued: 09/04/2007
• Est. Priority Date: 04/23/2004
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Laboratories of America Incorporated (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Voutsas, Apostolos T., Schuele, Paul J.
• Primary Examiner(s): Pert; Evan
• Assistant Examiner(s): TRAN, TAN N
• Application Number:
  US11/261,194
• Publication Number:
  US 20060049461A1
• Time in Patent Office: 676 Days
• Field of Search: None
• US Class Current: 257/135
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 29/78624 the source and the drain regions being asymmetrical
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate

Abstract

A vertical thin-film transistor (V-TFT) is provided along with a method for forming the V-TFT. The method comprises: providing a substrate made from a material such as Si, quartz, glass, or plastic; conformally depositing an insulating layer overlying the substrate; forming a gate, having sidewalls and a thickness, overlying a substrate insulation layer; forming a gate oxide layer overlying the gate sidewalls, and a gate insulation layer overlying the gate top surface; etching the exposed substrate insulation layer; forming a first source/drain region overlying the gate insulation layer; forming a second source/drain region overlying the substrate insulation layer, adjacent a first gate sidewall; and, forming a channel region overlying the first gate sidewall with a channel length about equal to the thickness of the gate, interposed between the first and second source/drain regions.

Claims

1. A vertical thin film transistor (V-TFT), the transistor comprising:

a substrate;

a substrate insulation layer overlying the substrate;

a gate, having sidewalls and a top surface, overlying the substrate insulation layer;

a gate insulation layer overlying the gate top surface;

a first source/drain region overlying the gate insulation layer;

a second source/drain region overlying the substrate insulation layer, adjacent a first gate sidewall;

a channel region overlying the first gate sidewall, interposed between the first and second source/drain regions;

a Vt adjust implant in the channel region; and

,

wherein the first and second source/drain regions are crystallized Si having a thickness in the range of 300 to 1000 Å

.

2. The transistor of claim 1 wherein the gate has a first thickness;

and,

wherein the channel region has a channel length about equal to the first thickness.

3. The transistor of claim 2 wherein the gate first thickness is in the range of 1000 to 6000 Å

.

4. The transistor of claim 1 further comprising:

a lightly doped drain (LDD) in the channel region adjacent the first source/drain region.

5. The transistor of claim 1 wherein the substrate is a material selected from group including Si, quartz, glass, and plastic;

and,

wherein the substrate insulation layer is a material selected from the group including SiO2, SiO2/Si3N4/SiO2, and organic insulators such as polyimide.

6. The transistor of claim 1 wherein the substrate insulation layer includes a recess formed in the substrate insulation layer adjacent the first gate sidewall;

and,

wherein the channel region extends into the substrate insulation layer recess.

7. The transistor of claim 1 wherein the gate is a doped Si material.

8. The transistor of claim 7 further comprising:

oxidized Si gate sidewall insulators; and

,

wherein the gate insulation layer is a material selected from the group including SiO2 and Si3N4, having a thickness in the range of 25 to 500 Å

.

9. The transistor of claim 1 wherein the gate is a metal material selected from the group including W and TiN.

10. The transistor of claim 1 wherein the first and second source/drain regions include Ni impurities.

11. The transistor of claim 1 further comprising:

an oxide spacer overlying the channels region, interposed between the first and second source/drain regions.

12. The transistor of claim 1 further comprising:

silicide metal regions, selected from the group of materials including Ni, Ti, and Co, formed in the first and second source/drain regions.

13. The transistor of claim 1 further comprising:

an interlevel dielectric (ILD) overlying the transistor; and

,

interconnects through the ILD to the first source/drain region, the second source/drain region, and the gate.

14. The transistor of claim 1 further comprising:

a third source/drain region overlying the substrate insulation layer, adjacent a second gate sidewall; and

,

a channel region overlying the second gate sidewall, interposed between the first source/drain region and the third source/drain region adjacent the second gate sidewall.