Narrow ultra wideband pulse generator

• US 7,265,598 B2
• Filed: 06/28/2005
• Issued: 09/04/2007
• Est. Priority Date: 05/25/2005
• Status: Active Grant

• Current Assignee: Rohde & Schwarz GmbH & Company KG
• Original Assignee: Camero-Tech, Ltd. (SK Group)
• Inventors: Kabelly, Moti, Keren, Yossi
• Primary Examiner(s): LE, DINH THANH
• Application Number:
  US11/167,599
• Publication Number:
  US 20060267652A1
• Time in Patent Office: 798 Days
• Field of Search: 327172-175, 327/119, 327/165, 327/164, 327/189, 342 82- 85
• US Class Current: 327/189
• CPC Class Codes: H03K 3/33 by the use, as active elements, of semiconductor devices exhibiting hole storage or enhancement effect

Abstract

A circuitry for generating a narrow impulse including an input device coupled to a matching circuitry that is coupled to a step recovery diode (SRD). The input device is configured to receive a succession of digital input signals, each characterized by having high level and low level portions. The signals having less than 50% duty cycle. The input device is configured to drive forward the SRD through the matching circuitry during the high level portion of the digital signal, whereby the SRD stores sufficient power for generating the narrow impulse following the falling edge of the high level portion of the digital input signal.

Claims

1. A circuitry for generating a narrow impulse, for use in Ultra Wide Band (UWB) radar transmission, comprising:

an input device coupled to a matching circuitry that is coupled to a step recovery diode (SRD);

said input device comprising first and second switching transistors, at least said second transistor having a control electrode and each of said transistors being DC coupled to said SRD, and said input device being configured to receive a succession of digital input signals, each characterized by having high level and low level portions, the signals having less than 50% duty cycle;

said input device further being configured to charge said SRD through said first transistor and to discharge said SRD through said second transistor for a short period of time by AC coupling said control electrode of said second transistor to an inverted digital input signal, said input device being configured to drive forward said SRD through the matching circuitry during the high level portion of said digital signal, whereby said SRD stores sufficient charge for generating said narrow impulse substantially following the falling edge of the high level portion of said digital input signal.

2. The circuitry according to claim 1, wherein said narrow impulse falls in the range of 3-10 Ghz.

3. The circuitry of claim 1, wherein said digital input signal having a repetition rate that falls in the range of 1-20 MHz.

4. The circuitry of claim 1, wherein said digital input signal has a time period of 15 nanoseconds or more.

5. The circuitry of claim 1, further comprising an output equalizing filter coupled to said SRD for outputting the generated impulse.

6. The circuitry of claim 1, wherein at least one of said transistors is a bi-polar transistor.

7. The circuitry of claim 1, wherein at least one of said transistors is a FET.

8. The circuitry of claim 1, wherein said input device includes a logical gate.

9. The circuitry of claim 1, wherein said circuitry is fitted in a comb generator.

10. The circuitry of claim 1, wherein said circuitry is fitted in a frequency multiplier.

11. The circuitry of claim 1, wherein said circuitry is fitted in a device for imaging through a wall.

12. The circuitry of claim 1, for use in a low power consumption application.

13. A circuitry for generating a narrow impulse, for use in Ultra Wide Band (UWB) radar transmission, comprising an input device coupled to a matching circuitry that is coupled to a step recovery diode (SRD);

said input device comprising first and second switching transistors, at least said second transistor having a control electrode and each of said transistors being DC coupled to said SRD, and said input device isbeing responsive to said input signal for charging said SRD through said first transistor and discharging said SRD through said second transistor for a short period of time by AC coupling of said control electrode of said second transistor to an inverted digital input pulse; and

wherein said input device is capable of driving forward SRD for a minimal duration for storing sufficient energy, for generating the narrow impulse.

14. The circuitry according to claim 13, wherein said narrow impulse falls in the range of 3-10 GHz.

15. The circuitry of claim 13, wherein said digital input signal having a repetition rate that falls in the range of 1-20 Mhz.

16. The circuitry of claim 13, wherein said digital input signal has a time period of 15 nanoseconds or more.

17. The circuitry of claim 13, further comprising an output equalizing filter coupled to said SRD for outputting generated impulse.

18. The circuitry of claim 13, wherein said circuitry is fitted in a device for imaging through a wall.