Voltage sustaining layer with opposite-doped islands for semiconductor power devices

• US 7,271,067 B2
• Filed: 03/01/2006
• Issued: 09/18/2007
• Est. Priority Date: 10/29/1993
• Status: Expired due to Fees

• Current Assignee: Third Dimension Semiconductor Incorporated
• Original Assignee: Third Dimension Semiconductor Incorporated
• Inventors: Chen, Xing-Bi
• Primary Examiner(s): COLEMAN, WILLIAM D
• Application Number:
  US11/365,223
• Publication Number:
  US 20060177995A1
• Time in Patent Office: 566 Days
• Field of Search: 438/137, 438/139, 438/140, 438/268, 438/269
• US Class Current: 438/269
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0821 Collector regions of bipolar transistors
• CPC Class Codes: H01L 29/73 Bipolar junction transistors
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7722 using static field induced regions, e.g. SIT, PBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/861 Diodes

Abstract

A semiconductor high-voltage device comprising a voltage sustaining layer between a n+-region and a p+-region is provided, which is a uniformly doped n (or p)-layer containing a plurality of floating p (or n)-islands. The effect of the floating islands is to absorb a large part of the electric flux when the layer is fully depleted under high reverse bias voltage so as the peak field is not increased when the doping concentration of voltage sustaining layer is increased. Therefore, the thickness and the specific on-resistance of the voltage sustaining layer for a given breakdown voltage can be much lower than those of a conventional voltage sustaining layer with the same breakdown voltage. By using the voltage sustaining layer of this invention, various high voltage devices can be made with better relation between specific on-resistance and breakdown voltage.

Claims

1. A method of manufacturing a semiconductor device comprising:

preparing a semiconductor wafer with a substrate of a first conductivity type;

forming a first epitaxial layer of the first conductivity type on the substrate, the first epitaxial layer having a first thickness;

growing a first oxide layer on the first epitaxial layer;

masking the first oxide layer;

ion implanting to create at least one embedded island of dopant of the second conductivity type in the first epitaxial layer;

removing the first oxide layer; and

forming a final epitaxial layer of the first conductivity type on the first epitaxial layer, the second epitaxial layer having the first thickness plus a thickness equal to the depth of the embedded islands of the second conductivity type.

2. The method according to claim 1, further comprising:

growing a second oxide layer on the second epitaxial layer;

masking the second oxide layer; and

ion implanting to create at least a single embedded region of the second conductivity type extending into the second epitaxial layer.

3. A method of manufacturing a semiconductor device comprising:

preparing a semiconductor wafer with a substrate of a first conductivity type;

forming a first epitaxial layer of the first conductivity type on the substrate, the first epitaxial layer having a first thickness;

growing a first oxide layer on the first epitaxial layer;

masking the first oxide layer;

ion implanting to create at least one embedded island of dopant of the second conductivity type in the first epitaxial layer;

removing the first oxide layer; and

forming a second epitaxial layer of the first conductivity type on the first epitaxial layer, the second epitaxial layer having the first thickness plus a thickness equal to the depth of the body region of a vertical diffusion metal oxide semiconductor transistor.

4. The method according to claim 3 further comprising:

growing a second oxide layer on the second epitaxial layer;

masking the second oxide layer; and

ion implanting to create at least one embedded region of the second conductivity type extending into the second epitaxial layer.

5. A method of manufacturing a semiconductor device comprising:

preparing a semiconductor wafer with a substrate of a first conductivity type having a buffer layer of the first conductivity type;

forming a first epitaxial layer of the first conductivity type on the substrate, the first epitaxial layer having a first thickness;

growing a first oxide layer on the first epitaxial layer;

masking the first oxide layer;

ion implanting to create at least one embedded island of dopant of the second conductivity type in the first epitaxial layer;

removing the first oxide layer; and

forming a second epitaxial layer of the first conductivity type on the first epitaxial layer, the second epitaxial layer having the first thickness plus a thickness equal to the depth of the body region of an insulated gate bipolar transistor.

6. The method according to claim 5 further comprising:

growing a second oxide layer on the second epitaxial layer;

masking the second oxide layer; and

ion implanting to create at least one embedded region of the second conductivity type extending into the second epitaxial layer.