AM data recovery circuit

• US 7,274,921 B2
• Filed: 12/02/2004
• Issued: 09/25/2007
• Est. Priority Date: 04/09/2002
• Status: Expired due to Term

• Current Assignee: Xueshan Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: MStar Semiconductor Incorporated (MediaTek, Inc.)
• Inventors: Smith, Sterling, Yung, Henry Tin-Hang
• Primary Examiner(s): NGUYEN, MATTHEW VAN
• Application Number:
  US11/001,133
• Publication Number:
  US 20050104573A1
• Time in Patent Office: 1,027 Days
• Field of Search: 455/227, 455/229, 455/254, 455/280, 455/287, 455/284, 455/291, 455/293, 455/313, 455/314, 455/323, 455/325, 455/333, 455/337, 455/343.1, 323/312, 323/313, 323/315
• US Class Current: 455/313
• CPC Class Codes: G06K 19/0713 the arrangement including a power charge pump
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
• CPC Class Codes: G11C 5/142 Contactless power supplies, e.g. RF, induction, or IR
• CPC Class Codes: H04B 5/77 for interrogation
• CPC Class Codes: H04B 7/086 using weights depending on external parameters, e.g. direction of arrival [DOA], predetermined weights or beamforming
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

The present invention provides a passive RFID chip with on-chip charge pumps for generating electrical power for the chip from radio frequencies. The passive RFID chip comprises an analog portion and a digital portion. The analog portion primarily comprises a voltage sensor and an AM data detector. The digital portion comprises a state machine digital logic controller. Incoming RF signals enter the chip via external antennas. The RF signals are converted into regulated DC signals by RF-DC converters with the voltage sensor. The RF-DC converters provide power for all the on-chip components and hence the chip does not require external power supply. The incoming RF signals are demodulated by demodulators and enter the AM data detector where the envelope transitions are detected. A voltage alarm is provided to ensure the voltage level does not drop below an operational level of the chip. The logic signals and programming data are controlled by the state machine digital logic controller and the timing signals are provided by an on-chip oscillator.

Claims

1. An AM data recovery circuit, comprising:

a demodulator for converting an incoming RF signal at an input node to a voltage signal at an output node;

a current-mode data detector for converting said voltage signal into a current signal responsive to the power at said output node of said demodulator and providing a feedback signal responsive to said current signal; and

a power-limiting device coupled in parallel to said demodulator to control the power at said output node of said demodulator responsive to said feedback signal.

2. The AM data recovery circuit as claimed in claim 1, further comprising a low pass filter for generating a control signal responsive to said feedback signal to control said power-limiting device.

3. The AM data recovery circuit as claimed in claim 1, wherein said power limiting device is a shunt element.

4. The AM data recovery circuit as claimed in claim 1, wherein said power limiting device is a variable resistance element.

5. The AM data recovery circuit as claimed in claim 1, wherein said demodulator is coupled to a first antenna with a first orientation for receiving said incoming RF signal.

6. The AM data recovery circuit as claimed in claim 3, wherein said shunt element is an NMOS transistor with a gate to be controlled by said control signal.

7. The AM data recovery circuit as claimed in claim 5, further comprising another demodulator, coupled to said demodulator at said output node.

8. The AM data recovery circuit as claimed in claim 7, wherein said another demodulator is coupled to a second antenna with a second orientation for receiving another incoming RF signal.

9. The AM data recovery circuit as claimed in claim 8, wherein said demodulator and said another demodulator convert said incoming RF signal and said another incoming RF signal to said voltage signal at said output node.

10. The AM data recovery circuit as claimed in claim 1, wherein the current signal is proportional to the power at said output node of said demodulator.

11. The AM data recovery circuit as claimed in claim 1, wherein the power limiting device acts to stabilize the average power output of both the data demodulator and a power conversion demodulator connected to same RF input node.

12. The AM data recovery circuit as claimed in claim 1, wherein the feedback signal is responsive to the difference between a reference value and the current signal.

13. The AM data recovery circuit as claimed in claim 1, wherein the energy recovered from the input RF is used to power the circuits to recover the digital data.

14. The AM data recovery circuit as claimed in claim 1, where said modulator and said current-mode data detector are integrated on a single substrate.

15. The AM data recovery circuit as claimed in claim 1, wherein no direct coupled energy source is connected to the system.

16. The AM data recovery circuit as claimed in claim 1, wherein said demodulator circuit is designed to operate with the frequency of said RF signal greater than 100 MHz.

17. An AM data recovery circuit, comprising:

a demodulator for converting an incoming RF signal at an input node to a voltage signal at an output node;

a voltage to current converter for converting said voltage signal into a current signal responsive to the power at said output node of said demodulator;

a baseband data recovery circuit for converting said current signal to a digital data signal; and

a power control circuit responsive to said current signal;

wherein said power at said output node of said demodulator is responsive to the envelope of said incoming RF signal.

18. The AM data recovery circuit as claimed in claim 17, wherein the power to operate said AM data recovery circuit is extracted from said RF signal at said RF input node.

19. The AM data recovery circuit as claimed in claim 17, wherein said power control circuit comprises a first control signal responsive to the difference between said current signal and a reference value;

and a low pass filter for generating a second control signal in response to said first control signal; and

a power-limiting circuit coupled to said demodulator to control the power at said output node of said demodulator in response to said second control signal.

20. The AM data recovery circuit as claimed in claim 17, where the output current is nearly proportional to the power output of the demodulator.

21. The AM data recovery circuit as claimed in claim 19, further comprising a second demodulator circuit coupled to same RF input node, wherein the said power limiting circuit acts to stabilize the power output of the said second demodulator circuit.

22. The AM data recovery circuit as claimed in claim 21, wherein said power output of said second demodulator circuit supplies the power to operate said AM data recovery circuit.

23. The AM data recovery circuit as claimed in claim 17, wherein a data memory, an RF transmitter, and a digital state machine are integrated on the same substrate as said AM data recovery circuit.

24. The AM data recovery circuit as claimed in claim 23, wherein the power to operate said circuits on said substrate is extracted from said RF signal at said RF input node.

25. The AM data recovery circuit as claimed in claim 18, wherein said demodulator circuit is designed to operate with the frequency of said RF signal greater than 100 MHz.