Probe card assembly with dielectric structure

• US 7,279,911 B2
• Filed: 05/03/2005
• Issued: 10/09/2007
• Est. Priority Date: 05/03/2005
• Status: Expired due to Fees

• Current Assignee: SV Probe Pte Ltd. (Nidec Corporation)
• Original Assignee: SV Probe Pte Ltd. (Nidec Corporation)
• Inventors: Tunaboylu, Bahadir, Kilicaslan, Habib
• Primary Examiner(s): PATEL, PARESH H
• Application Number:
  US11/121,241
• Publication Number:
  US 20060250150A1
• Time in Patent Office: 889 Days
• Field of Search: None
• US Class Current: 324/756.03
• CPC Class Codes: G01R 1/07378 using an intermediate adapter, e.g. space transformers G01R1/07371 takes precedence

Abstract

A probe card assembly for providing electrical interconnection between a semiconductor device to be tested and a test system is provided. The probe card assembly includes a plurality of probes supported by a support substrate, each of the plurality of probes including an end portion extending away from the support substrate. The end portion is configured to be electrically connected to a semiconductor device to be tested. The probe card assembly also includes a dielectric sheet positioned between the support substrate and the end portion of the plurality of probes such that the probes extend through apertures defined by the dielectric sheet.

Claims

1. A probe card assembly for providing electrical interconnection between a semiconductor device to be tested and a test system, the probe card assembly comprising:

a plurality of probes supported by a support substrate, each of the plurality of probes including an end portion extending away from the support substrate, the end portion being configured to be electrically connected to a semiconductor device to be tested;

a dielectric sheet positioned between the support substrate and the end portion of the plurality of probes such that the probes extend through apertures defined by the dielectric sheet, wherein one or more of the apertures are dimensioned such that one or more of the plurality of probes extend through and do not contact the dielectric sheet adjacent a respective aperture when the probe card assembly is in a test position with respect to the semiconductor device to be tested; and

an electrically conductive layer disposed on the dielectric sheet, the electrically conductive layer being spaced from the apertures.

2. The probe card assembly according to claim 1, wherein the plurality of probes comprise signal probes and power probes, and wherein the apertures through which one or more of the power probes extend are dimensioned such that the one or more power probes contact the dielectric sheet adjacent a respective aperture when the probe card assembly is in a test position with respect to the semiconductor device to be tested.

3. The probe card assembly according to claim 1, wherein the plurality of probes comprise signal probes and power probes, and wherein the apertures through which one or more of the signal probes extend are dimensioned such that the one or more signal probes do not contact the dielectric sheet adjacent a respective aperture when the probe card assembly is in a test position with respect to the semiconductor device to be tested.

4. The probe card assembly according to claim 1, wherein the electrically conductive layer covers only specified portions of the dielectric sheet.

5. The probe card assembly according to claim 1, wherein the electrically conductive layer is disposed on a side of the dielectric sheet configured to be adjacent the semiconductor device to be tested.

6. The probe card assembly according to claim 1, wherein the plurality of probes comprise signal probes and power probes, wherein the apertures through which one or more of the power probes extend are dimensioned such that the one or more power probes contact the dielectric sheet adjacent a respective aperture when the probe card assembly is in a test position with respect to the semiconductor device to be tested, and wherein the apertures through which one or more of the signal probes extend are dimensioned such that the one or more signal probes do not contact the dielectric sheet adjacent a respective aperture when the probe card assembly is in the test position.

7. The probe card assembly according to claim 6, wherein the electrically conductive layer is spaced from the apertures such that the power probes do not contact the electrically conductive layer when the probe card assembly is in the test position.

8. The probe card assembly according to claim 1, wherein the dielectric sheet has a dielectric coefficient of at least about 10.

9. The probe card assembly of claim 1, wherein the dielectric sheet has a dielectric constant of at least about 100.

10. The probe card assembly according to claim 1 wherein the support substrate is a space transformer.