Circuit arrangement for operating at least one light-emitting diode

• US 7,280,375 B2
• Filed: 10/08/2003
• Issued: 10/09/2007
• Est. Priority Date: 11/11/2002
• Status: Expired due to Fees

• Current Assignee: Conti Temic Microelectronic GmbH (Continental AG)
• Original Assignee: Conti Temic Microelectronic GmbH (Continental AG)
• Inventors: Joos, Ulrich
• Primary Examiner(s): Philogene; Haissa
• Application Number:
  US10/532,544
• Publication Number:
  US 20050269956A1
• Time in Patent Office: 1,462 Days
• Field of Search: 363/21.04, 363/21.1, 363/21.18, 363 24- 26, 363/31, 363/16, 363/17, 363/89, 363/63, 363/56.02, 363/56.01, 363/98, 363/108, 363/109, 362/227, 362/800, 362/265, 315/291, 315/209.R, 315/200.R, 315/224, 315/216, 315/226, 315/77, 315/82
• US Class Current: 363/17
• CPC Class Codes: H05B 45/325 Pulse-width modulation [PWM]
• CPC Class Codes: H05B 45/37 Converter circuits
• CPC Class Codes: H05B 45/39 Circuits containing inverter bridges
• CPC Class Codes: H05B 45/50 responsive to malfunctions or undesirable behaviour of LEDs; responsive to LED life; Protective circuits
• CPC Class Codes: Y02B 20/30 Semiconductor lamps, e.g. solid state lamps [SSL] light emitting diodes [LED] or organic LED [OLED]
• CPC Class Codes: Y10S 362/80 Light emitting diode

Abstract

A circuit arrangement is for operating at least one light-emitting diode LED in an electrical circuit at a service voltage greater than the forward voltage of the at least one light-emitting diode. The light-emitting diode is PWM-controlled. The circuit includes reactances that are connected in series at both connections of the light-emitting diode, an additional switching arrangement between the terminals, and a full-wave rectifier circuit, such that the circuit is protected against short-circuits on the service voltage and on ground while the LED can continue to be triggered.

Claims

1. A circuit arrangement for operating at least one light-emitting diode (LED) in an electrical circuit at a service voltage (UB), which is greater than the forward voltage of the at least one light-emitting diode (LED) which is to be operated,

wherein adjustment of a current flowing through the light-emitting diode (LED) is performed by means of pulse-width modulation of a first switching means (S1), which is switched between a first terminal of the service voltage (UB) and the light-emitting diode LED,

wherein between the first terminal of the service voltage (UB) and the at least one light-emitting diode (LED) a first reactance formed by a first resistance (R1) and a first capacitor (C1) is arranged,

characterized in that

the at least one light-emitting diode (LED) is connected via a second reactance formed by a second resistance (R2) and a second capacitor (C2) to a second terminal of the service voltage,

between the two connections of the at least one light-emitting diode (LED) and the two reactances (R1-C1, R2-C2) a full-wave rectifier diode bridge of four diodes (D1, D2, D3, D4) being switched, and

at a tap between the first switching means (S1) and the at least one light-emitting diode (LED) a connection, switchable via a second switching means (S2), to the second terminal of the service voltage exists, the second switching means (S2) being operated in push-pull action to the first switching means (S1).

2. A circuit arrangement according to claim 1, characterized in that the service voltage is a d.c. voltage and in that the service voltage is applied at the first terminal and a ground potential is applied at the second terminal and in that the full-wave rectifier circuit is formed of four diodes (D1, D2, D3, D4), the diodes being interconnected as follows:

the first diode (D1) is polarized in forward direction and is switched between the first reactance (R1-C1) and the positive terminal (U_LED+) of the light-emitting diode (LED),

the second diode (D2) is polarized in the inverse direction and is switched between the first reactance (R1-C1) and the negative terminal (U_LED−

) of the light-emitting diode (LED),

the third diode (D3) is polarized in forward direction and is switched between the second reactance (R2-C2) and the negative terminal (U_LED−

) of the light-emitting diode (LED),

the fourth diode (D4) is polarized in the inverse direction and is switched between the second reactance (R2-C2) and the positive terminal (U_LED+) of the light-emitting diode (LED).

3. A circuit arrangement according to claim 2, characterized in that for level adaptation, the pulse-width modulated signal (PWM) is connected to the base of a level transistor (T0) of the circuit arrangement, of which the collector is connected to the ground (GND) and its emitter is connected to the service voltage (UB) as well as to the bases of a first White'"'"'s emitter follower for the purpose of current amplification, which first White'"'"'s emitter follower is substantially composed of a first NPN transistor (T1) and a first PNP transistor (T2), the emitter of the NPN transistor (T1) being connected to the emitter of the PNP transistor (T2) and to the first resistance (R1), and the collector of the NPN transistor (T1) being connected to the service voltage (UB), and the collector of the PNP transistor (T2) being connected to the ground (GND).

4. A circuit arrangement according to claim 3, characterized in that for limiting a rise time of the signal (PWM) modulated in pulse-width, and amplified in current, a second White'"'"'s emitter follower from a second NPN transistor (T3) and a second PNP transistor (T4) is connected between the first resistance (R1) and via a further resistance (R0) to the emitter of the first White'"'"'s emitter follower, between the further resistance (R0) and the bases of the second White'"'"'s emitter follower a second capacitor (C0) being connected to the ground (GND).

5. A circuit arrangement according to claim 3, characterized in that at least one of the transistors is embodied as a metal-oxide field-effect transistor.

6. A circuit arrangement according to claim 4, characterized in that the level transistor (T0) and/or the first NPN transistor (T1) and/or the first PNP transistor (T2) and/or the second NPN transistor (T3) and/or the second PNP transistor (T4) are embodied as metal-oxide field-effect transistors.