Deep power saving by disabling clock distribution without separate clock distribution for power management logic

• US 7,284,138 B2
• Filed: 12/02/2004
• Issued: 10/16/2007
• Est. Priority Date: 12/02/2004
• Status: Expired due to Fees

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Wang, Michael Fan, Weitzel, Stephen Douglas, Stasiak, Daniel Lawrence, Riley, Mack Wayne
• Primary Examiner(s): Lee; Thomas
• Assistant Examiner(s): BOCHICCO, BRIAN J
• Application Number:
  US11/002,551
• Publication Number:
  US 20060123261A1
• Time in Patent Office: 1,048 Days
• Field of Search: 713300-340
• US Class Current: 713/322
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An apparatus, a method, and a computer program are provided to disable clock distribution. In microprocessors, the clock distribution system can account for a substantial amount of power consumption. Disabling the clock distribution system, however, has been difficult because of the usual requirement for a separate clock for control logic. Therefore, combinational logic can be employed to disrupt the clock distribution and allow a processor to be awakened without a need for a separate clock.

Claims

1. An apparatus, comprising:

a system logic unit coupled to receive a clock (CLK) signal and a power save mode acknowledge (PSM_ACK) signal, wherein the PSM_ACK signal is asserted in a power saving mode, and wherein the system logic unit is configured to perform a function dependent upon the CLK signal and to produce a clock enable (CLK_EN) signal in response to the PSM_ACK signal;

enable logic coupled to receive the PSM_ACK signal and the CLK_EN signal, and configured to selectively produce one of a MUX enable signal and a MUX disable signal dependent upon a selected combination of the PSM_ACK signal and the CLK_EN signal;

a multiplexer (MUX) coupled to the enable logic and configured to receive the MUX enable signal and to select one of a plurality of PLL frequency inputs, and to generate a CLK signal in response to the selected one of a plurality of PLL frequency inputs and the MUX enable signal; and

a phased locked loop (PLL) unit coupled to the MUX and a reference clock (REF_CLK) signal, and configured to use the REF_CLK signal to produce the plurality of PLL frequency inputs to the MUX.

2. The apparatus of claim 1, wherein the apparatus is a processor.

3. The apparatus of claim 1, wherein the system logic unit comprises pervasive logic coupled to receive the PSM_ACK signal and configured to produce the CLK_EN signal in response to the PSM_ACK signal.

4. The apparatus of claim 1, wherein the enable logic is configured to deassert the MUX enable signal in the event the PSM_ACK signal is asserted and the CLK_EN signal is asserted.

5. The apparatus of claim 1, wherein the enable logic comprises an AND logic gate.

6. A method for selectively producing a clock (CLK) signal, comprising:

receiving a power save mode acknowledge (PSM_ACK) signal and responding to the PSM_ACK signal by producing a clock enable (CLK_EN) signal, wherein the PSM_ACK signal is asserted in a power saving mode;

receiving the PSM_ACK signal and the CLK_EN signal and using a selected combination of the received PSM_ACK and CLK_EN signals to selectively produce one of a MUX enable signal and a MUX disable signal;

receiving a reference clock (REF_CLK) signal and using the REF_CLK signal to produce a plurality of phased lock loop (PLL) signals;

selecting one of the plurality of PLL signals in response to a frequency select (FREQ_SEL) signal; and

generating a clock signal (CLK) based on the selected one of the plurality of PLL signals and the MUX enable signal.