Correlated double sampling variable gain amplifier circuit for use in a digital camera
First Claim
1. A correlated double sampler and variable gain amplifier (CDSVGA) circuit for receiving CCD data, comprising:
- a first fixed capacitor for receiving CCD data;
a first amplifier connected to said first fixed capacitor for amplifying CCD data, said first amplifier connected to said first fixed capacitor;
a first variable capacitor connected in parallel with said first amplifier;
a first switch connected in parallel with said first variable capacitor, said first switch being clocked at a first clock phase;
a second variable capacitor connected to said first amplifier;
a second amplifier connected to said second variable capacitor;
a second fixed capacitor connected in parallel with said second amplifier; and
a second switch connected in parallel with said second fixed amplifier;
said second switch being clocked at a second clock phase; and
wherein a total gain of the CDSVGA circuit is a product of a divided value derived from a value of the first fixed capacitor divided by a value of the second fixed capacitor and another divided value derived from a value of the second variable capacitor divided by a value of the first variable capacitor.
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Accused Products
Abstract
An image processor system for a charge coupled device (CCD) or CMOS imaging system includes a correlated double sample and variable gain (CDSVGA) circuit for receiving data from a CCD system and an automatic gain control (AGC) circuit which first controls gain by adjusting said CCD system and then for yet a higher gain level makes gain adjustments in said CDSVGA circuit AND a digital gain circuit to produce a combined target gain level. A processing system for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to said CDS circuit, a digital gain circuit (DGC) coupled to said ADC, and an automatic gain control (AGC) circuit coupled to said DGC for controlling the CDS circuit and the DGC. The processing circuitry includes an analog front end and a digital signal processing system for capturing full motion video and outputting a CCIR 601 4:2:2 YCrCb video data output for presentation on a user selected display.
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Citations
12 Claims
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1. A correlated double sampler and variable gain amplifier (CDSVGA) circuit for receiving CCD data, comprising:
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a first fixed capacitor for receiving CCD data; a first amplifier connected to said first fixed capacitor for amplifying CCD data, said first amplifier connected to said first fixed capacitor; a first variable capacitor connected in parallel with said first amplifier; a first switch connected in parallel with said first variable capacitor, said first switch being clocked at a first clock phase; a second variable capacitor connected to said first amplifier; a second amplifier connected to said second variable capacitor; a second fixed capacitor connected in parallel with said second amplifier; and a second switch connected in parallel with said second fixed amplifier;
said second switch being clocked at a second clock phase; andwherein a total gain of the CDSVGA circuit is a product of a divided value derived from a value of the first fixed capacitor divided by a value of the second fixed capacitor and another divided value derived from a value of the second variable capacitor divided by a value of the first variable capacitor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A correlated double sampler and variable gain amplifier (CDSVGA) circuit for receiving CCD data, comprising:
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a first fixed capacitor for receiving CCD data; a first amplifier connected to said first fixed capacitor for amplifying CCD data, said first amplifier connected to said first fixed capacitor; a first variable capacitor connected in parallel with said first amplifier; a first switch connected in parallel with said first variable capacitor, said first switch being clocked at a first clock phase; a second variable capacitor connected to said first amplifier; a second amplifier connected to said second variable capacitor; a second fixed capacitor connected in parallel with said second amplifier; and a second switch connected in parallel with said second fixed amplifier;
said second switch being clocked at a second clock phase; andwherein the first fixed capacitor, the first amplifier, the first variable capacitor, and the first switch perform correlated double sampling by sampling a feed-through level across the first fixed capacitor when the first clock phase is high and an amplifier output of the first amplifier follows an input gain in accordance with a divided capacitor value that is derived from a negative of a value of the first fixed capacitor divided by a value of the first variable capacitor when the first clock phase is low.
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11. A correlated double sampler and variable gain amplifier (CDSVGA) circuit for receiving CCD data, comprising:
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a first fixed capacitor for receiving CCD data; a first amplifier connected to said first fixed capacitor for amplifying CCD data, said first amplifier connected to said first fixed capacitor; a first variable capacitor connected in parallel with said first amplifier; a first switch connected in parallel with said first variable capacitor, said first switch being clocked at a first clock phase; a second variable capacitor connected to said first amplifier; a second amplifier connected to said second variable capacitor; a second fixed capacitor connected in parallel with said second amplifier; and a second switch connected in parallel with said second fixed amplifier;
said second switch being clocked at a second clock phase; andwherein the second fixed capacitor, the second amplifier, the second variable capacitor, and the second switch perrorm correlated double sampling by sampling a feed-through level across the second fixed capacitor when the second clock phase is high and an amplifier output of the second amplifier follows an input gain in accordance with a divided capacitor value that is derived from a negative of a value of the second fixed capacitor divided by a value of the second variable capacitor when the second clock phase is low. - View Dependent Claims (12)
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Specification