Method for eliminating crosstalk in a metal programmable read only memory

• US 7,289,376 B2
• Filed: 08/10/2005
• Issued: 10/30/2007
• Est. Priority Date: 12/30/2004
• Status: Expired due to Fees

• Current Assignee: National Chiao Tung University (Government of The Republic of China)
• Original Assignee: National Chiao Tung University (Government of The Republic of China)
• Inventors: Chang, Meng-Fan, Wen, Kuei-Ann
• Primary Examiner(s): NGUYEN, VAN THU T
• Application Number:
  US11/201,943
• Publication Number:
  US 20060146587A1
• Time in Patent Office: 811 Days
• Field of Search: 365/189.06 O, 365/203.X, 365/204.X, 365/230.04, 365/189.06, 365/203, 365/204
• US Class Current: 365/189.06
• CPC Class Codes: G11C 17/14 in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

The present invention provides a method for eliminating crosstalk (coupling noise) in a metal programmable read only memory. The metal programmable read only memory comprises a plurality of bit lines, a plurality of word lines, a plurality of precharge transistors, and a plurality of clamp transistors. When one of the bit lines is selected, bit lines adjacent to the selected bit line are fixed to a voltage value (VDD, GND or other voltages) by the clamp transistors. The clamping method can not cause voltage drops to the adjacent bit lines, and the crosstalk on the selected bit line can be eliminated simultaneously, so that the problem of read failures caused by the crosstalk in the high-speed metal programmable read only memory can be solved, and a higher speed can be reached.

Claims

1. A method for eliminating crosstalk, suitable for a metal programmable read only memory, the read only memory comprises:

a plurality of bit lines, each of which couples the drains of transistors together in the same column;

a plurality of word lines, each of which couples the gates of transistors together in the same row;

a plurality of precharge transistors, arranged on each of the bit lines, and the gates of which are coupled together by a precharge control line; and

a plurality of clamp transistors, arranged in matrix on each of the bit lines for clamping a constant voltage,

wherein when one of the bit lines is selected, bit lines adjacent to the selected bit line are fixed to a voltage value by the clamp transistors.

2. The method as claimed in claim 1, wherein the bit lines adjacent to the selected bit line are fixed to a voltage value by the clamp transistors during a word line pulse having a high logic level.

3. The method as claimed in claim 1, wherein the read only memory is a read only memory having a metal, contact-hole or via-hole programming layer.

4. The method as claimed in claim 1, wherein the bit lines have three states during data sensing phase:

selected-for-reading state, unselected-for-reading state, and clamping state.