Computing blending functions for the tiling of overlapped video projectors

• US 7,292,207 B1
• Filed: 08/27/2004
• Issued: 11/06/2007
• Est. Priority Date: 08/27/2004
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Naegle, Nathaniel David, Castle, Clayton W.
• Primary Examiner(s): Nguyen; Kevin M.
• Application Number:
  US10/929,115
• Time in Patent Office: 1,166 Days
• Field of Search: 345/1.1, 345/1.3, 345/589, 345/639, 345/647, 348/580, 348/744, 348/383, 353/94
• US Class Current: 345/1.3
• CPC Class Codes: G09G 2320/0233 Improving the luminance or brightness uniformity across the screen
• CPC Class Codes: G09G 2340/10 Mixing of images, i.e. displayed pixel being the result of an operation, e.g. adding, on the corresponding input pixels
• CPC Class Codes: G09G 3/001 using specific devices not provided for in groups G09G3/02 - G09G3/36, e.g. using an intermediate record carrier such as a film slide; Projection systems; Display of non-alphanumerical information, solely or in combination with alphanumerical information, e.g. digital display on projected diapositive as background slide projectors per se G03B23/00 = 42 HP
• CPC Class Codes: H04N 9/3147 Multi-projection systems displays in general H04N9/12; video walls G06F3/1446, G09G2300/026
• CPC Class Codes: H04N 9/3182 Colour adjustment, e.g. white balance, shading or gamut white balance per se H04N9/73; control of amplitude of colour signals H04N9/68; colour control circuits for displays in general G09G5/02, G09G3/2003, G09G3/3607
• CPC Class Codes: H04N 9/3188 Scale or resolution adjustment scaling in general G06T3/40; resolution modifying circuits for displays in general G09G5/391

Abstract

A system for correcting the intensities of pixels supplied to a projector. An image generated by the projector has a number of regions formed by the overlapping of the image with one or more other images generated by one or more other projectors. The system includes: a first unit configured to generate a horizontal scaling value; a second unit configured to generate a vertical scaling value; a first multiplier configured to multiply the horizontal scaling value and the vertical scaling value to obtain a scaling coefficient, and a set of one or more additional multipliers configured to multiply components of an input pixel by the scaling coefficient to determine components for an output pixel. The first unit and second unit compute their respective scaling values in a way that allows for regions whose boundaries non-aligned in the vertical direction.

Claims

1. A system comprising:

a first unit configured to generate a horizontal scaling value;

a second unit configured to generate a vertical scaling value;

a first multiplier configured to multiply the horizontal scaling value and the vertical scaling value to obtain a scaling coefficient;

a set of one or more additional multipliers configured to multiply components of an input pixel by the scaling coefficient to determine components for an output pixel;

wherein the first unit is configured to compute an address U in the address space of a horizontal weight table, wherein the address U as a function of horizontal pixel index I is piecewise linear, wherein the first unit is configured to access stored values from the horizontal weight table using the address U and compute the horizontal scaling value based on the accessed values;

wherein the second unit is configured to compute an address V in the address space of a vertical weight table, wherein the address V as a function of vertical pixel index J is piecewise linear, wherein the second unit is configured to access stored values from the vertical weight table using the address V and compute the vertical scaling value based on the accessed values;

wherein the first unit is configured to vary the addresses U₀, U₁ and U₂ that bound the linear sections of the piecewise linear function as a function of the vertical pixel position.

2. The system of claim 1, wherein the first unit is configured to vary the addresses U₀, U₁ and U₂ by adding corresponding horizontal step values to the addresses U₀, U₁ and U₂ once per horizontal line.

3. The system of claim 2, wherein the horizontal step values are signed fixed-point quantities.

4. The system of claim 2,

wherein the first unit includes a first set of registers configured to store the values U₀, U₁ and U₂, a current address register, and a first multiplexer, wherein the first multiplexer is configured to select one of the values U₀, U₁, U₂ or the value of the current address register, wherein the output of the first multiplexer is the address U;

a first interpolation unit coupled to the output of the first multiplexer and configured to access values from the horizontal weight table and compute the horizontal scaling value based on the accessed values.

5. The system of claim 4, wherein the first interpolation unit is configured to access values located at [U] and [U+1] in the address space of the horizontal weight table and to interpolate between these values based on an alpha value equal to U−

[U], where [U] is the integer part of U.

6. The system of claim 4, wherein the first unit further includes a second set of registers, a second multiplexer and a first adder, wherein the second set of registers are configured to store horizontal step values Sx₀, Sx₁ and Sx₂, wherein the second multiplexer is configured to select one of the horizontal step values, wherein the first adder is coupled to receive the selected horizontal step value from the second multiplexer and the address U provided at the output of the first multiplexer, wherein the first adder is configured to add the selected horizontal step value to the address U to obtain an incremented value of the address U, wherein the current address register is coupled to receive the incremented value from the first adder.

7. The system of claim 6, wherein the first unit further includes a third set of registers, a third multiplexer and a second adder, wherein the third set of registers are configured to store increments dSx₀, dSx₁ and dSx₂ for the horizontal step values Sx₀, Sx₁ and Sx₂ respectively, wherein the third multiplexer is configured to select one of the increments dSx₀, dSx₁ and dSx₂, wherein the second adder is configured to receive the selected increment from the third multiplexer and the selected horizontal step value from the second multiplexer, wherein the adder is configured to add the selected increment and the selected horizontal step to obtain an incremented horizontal step, wherein each of the registers of the second set is coupled to receive the output of the second adder, wherein the first unit further includes a controller to direct loading of the incremented horizontal step into one of the registers of the second set.

8. The system of claim 7, wherein the controller is configured to control the selections of the first, second and third multiplexers, wherein the controller includes:

registers for storing current region widths XCnt1′

, XCnt2′ and

XCnt3′

,

a fourth multiplexer for selecting one of the current region widths, and

a first decrement unit for initializing a value XCnt with the selected one and decrementing the value XCnt down towards zero in response transitions of a pixel clock,

wherein the controller is configured to direct the first multiplexer to select the address U_K+1, when the value XCnt, which has been previously initialized with XCnt_K′

, K=0, 1 or 2, reaches zero.

9. The system of claim 8, wherein the controller is configured to direct the first multiplexer to select the input from the current address register when the value XCnt is not equal to zero.

10. The system of claim 8, wherein the controller is configured to add corresponding increments to the values XCnt1′

, XCnt2′ and

XCnt3′

once per line of video, wherein the increments are programmable by a host computer, wherein the increments are signed fixed-point quantities.

11. The system of claim 10, wherein the controller further includes:

registers configured to store width increments dXCnt1, dXCnt2 and dXCnt3,

a fifth multiplexer configured to select one of the width increments, and

an adder configured to receive the selected width increment from the fifth multiplexer and the selected current region width from the fourth multiplexer, wherein the adder is configured to add the selected width increment and the selected current region width to obtain an incremented region width, wherein the controller is configured to load the incremented region width into a corresponding one of the registers XCnt1′

, XCnt2′ and

XCnt3′

.

12. The system of claim 11, wherein the controller is configured to initialize the registers XCnt1′

, XCnt2′

, XCnt3′

with their corresponding initial values once per frame.

13. The system of claim 2,

wherein the second unit includes a fourth set of registers configured to store the values V₀, V₁ and V₂, a current address register, and a fourth multiplexer, wherein the fourth multiplexer is configured to select one of the values V₀, V₁, V₂ or the value of the current address register, wherein the output of the fourth multiplexer is the address V;

a second interpolation unit coupled to the output of the fourth multiplexer and configured to access values from the vertical weight table and compute the vertical scaling value based on the accessed values.

14. The system of claim 13, wherein the second interpolation unit is configured to access values located at [V] and [V+1] in the address space of the vertical weight table and to interpolate between these values based on an alpha value equal to V−

[V], where [V] is the integer part of V.

15. The system of claim 14, wherein the second unit further includes a fifth set of registers, a fifth multiplexer and a third adder, wherein the fifth set of registers are configured to store vertical step values Sy₀, Sy₁ and Sy₂, wherein the fifth multiplexer is configured to select one of the vertical step values, wherein the third adder is coupled to receive the selected vertical step value from the fifth multiplexer and the address V provided at the output of the fourth multiplexer, wherein the third adder is configured to add the selected vertical step value to the address V to obtain an incremented value of the address V, wherein the current address register is coupled to receive the incremented value from the third adder.

16. The system of claim 1, wherein the first unit and second unit operate in parallel.

17. The system of claim 1, wherein the horizontal weight table and the vertical weight table are programmable.

18. The system of claim of 1, wherein the horizontal weight table and the vertical weight table are loaded with corresponding sets of values to induce edge blending on the image generated by a first projector with respect to the overlapping images generated by one or more other projectors.

19. The system of claim 1, wherein the horizontal weight table and the vertical weight table are loaded with corresponding sets of values to induce hot spot correction on the image generated by a first projector.

20. A system for correcting the intensities of pixels supplied to a projector, wherein an image generated by the projector has a number of regions formed by the overlapping of the image with one or more other images generated by one or more other projectors, the system comprising:

a first unit configured to generate a horizontal scaling value;

a second unit configured to generate a vertical scaling value;

a first multiplier configured to multiply the horizontal scaling value and the vertical scaling value to obtain a scaling coefficient;

a set of one or more additional multipliers configured to multiply components of an input pixel by the scaling coefficient to determine components for an output pixel;

wherein the first unit includes a digital differential analyzer (DDA) to repeatedly increment an address U in the address space of the horizontal weight table, wherein a start value and an increment value used by the DDA changes varies between regions in the horizontal direction, wherein the boundaries between the regions are not vertically aligned;

wherein the second unit includes a second DDA to repeatedly increment an address V in the address space of the vertical weight table, wherein a start value and increment value used by the second DDA changes between regions in the vertical direction.