DRAM (Dynamic Random Access Memory) cells

• US 7,294,543 B2
• Filed: 03/22/2006
• Issued: 11/13/2007
• Est. Priority Date: 03/22/2006
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Khan, Babar Ali
• Primary Examiner(s): QUACH, TUAN N
• Application Number:
  US11/308,404
• Publication Number:
  US 20070222020A1
• Time in Patent Office: 601 Days
• Field of Search: 257/296, 257301-305, 257/E29.346, 257/E21.396, 438243-249, 438/386, 438389-392
• US Class Current: 438/243
• CPC Class Codes: H10B 12/0387 Making the trench

Abstract

A DRAM cell with a self-aligned gradient P-well and a method for forming the same. The DRAM cell includes (a) a semiconductor substrate; (b) an electrically conducting region including a first portion, a second portion, and a third portion; (c) a first doped semiconductor region wrapping around the first portion, but electrically insulated from the first portion by a capacitor dielectric layer; (d) a second doped semiconductor region wrapping around the second portion, but electrically insulated from the second portion by a collar dielectric layer. The second portion is on top of and electrically coupled to the first portion, and the third portion is on top of and electrically coupled to the second portion. The collar dielectric layer is in direct physical contact with the capacitor dielectric layer. When going away from the collar dielectric layer, a doping concentration of the second doped semiconductor region decreases.

Claims

1. A semiconductor fabrication method, comprising:

providing a semiconductor structure which includes;

(a) a semiconductor substrate,

(b) a trench in the semiconductor substrate,

wherein the trench comprises a side wall and a bottom wall, and

wherein the side wall comprises an upper side wall portion and a lower side wall portion;

forming a first doped semiconductor region and a second doped semiconductor region,

wherein the first doped semiconductor region (i) wraps around the lower side wall portion of the trench and (ii) abuts the bottom wall and the lower side wall portion of the trench,

wherein the second doped semiconductor region wraps around and abuts the upper side wall portion of the trench,

wherein the second doped semiconductor region is self-aligned to the first doped semiconductor region,

wherein the first doped semiconductor region comprises dopants electrically exhibiting a first doping polarity,

wherein the second doped semiconductor region comprises dopants electrically exhibiting a second doping polarity which is opposite to the first doping polarity, and

after said forming the first doped semiconductor region and the second doped semiconductor region is performed, forming a dielectric layer and an electrically conducting region in the trench,

wherein the dielectric layer is on the side wall and the bottom wall of the trench,

wherein the dielectric layer comprises a capacitor dielectric portion and a collar dielectric portion,

wherein the electrically conducting region comprises dopants of the first doping polarity,

wherein the electrically conducting region comprises a first portion, a second portion, and a third portion,

wherein the second portion is on top of and electrically coupled to the first portion, and the third portion is on top of and electrically coupled to the second portion, and

wherein when going from an interfacing surface of the collar dielectric portion and the second doped semiconductor region and away from the collar dielectric portion, a doping concentration of the second doped semiconductor region decreases.

2. The method of claim 1, wherein a thickness of the capacitor dielectric portion is essentially the same as or less than a thickness of the collar dielectric portion.

3. The method of claim 1, wherein the collar dielectric layer is formed by thermal oxidation and wherein the collar dielectric layer essentially does not contain dopants.

4. The method of claim 1, wherein said forming the electrically conducting region comprises:

forming the first portion of the electrically conducting region in the trench;

forming the second portion of the electrically conducting region on top of and electrically coupled to the first portion and in the trench; and

forming the third portion of the electrically conducting region on top of the second portion and in the trench.

5. The method of claim 1, wherein the collar dielectric portion is sandwiched between and electrically insulates the second doped semiconductor region and the second portion of the electrically conducting region.

6. The method of claim 1, wherein said forming the first doped semiconductor region and the second doped semiconductor region comprises:

forming a first doping source region on the lower side wall portion and the bottom wall of the trench, wherein the first doping source region comprises dopants of the first doping polarity;

after said forming the first doping source region is performed, forming a second doping source region on the upper side wall portion of the trench, wherein the second doping source region comprises dopants of the second doping polarity which is opposite to the first doping polarity; and

after said forming the second doping source region is performed, annealing the semiconductor structure to diffuse dopants simultaneously from the first and second doping source regions into the semiconductor substrate, resulting in the first doped semiconductor region and the second doped semiconductor region, respectively.

7. The method of claim 6,

wherein the first doping source region comprises arsenic silicate glass (ASG), and

wherein the second doping source region comprises boron silicate glass (BSG).

8. The method of claim 7,

wherein a doping concentration in the first doping source region is greater than a doping concentration in the second doping source region.

9. The method of claim 7, wherein said first and second doping source regions are removed after said annealing the semiconductor structure is performed.

10. The method of claim 1, wherein said forming the dielectric layer and the electrically conducting region comprises:

forming the capacitor dielectric portion on the lower side wall portion and the bottom wall of the trench;

then

forming a first portion of the electrically conducting region in the trench;

then

forming the collar dielectric portion on the upper side wall portion of the trench;

then

forming the second portion of the electrically conducting region on top of and electrically coupled to the first portion and in the trench, wherein the collar dielectric portion is sandwiched between the second portion of the electrically conducting region and the second doped semiconductor region; and

then

forming the third portion of the electrically conducting region on top of the second portion and in the trench.

11. The method of claim 10, further comprising forming a buried strap region,

wherein the buried strap region is in direct physical contact with both the third portion of the electrically conducting region and the second doped semiconductor region, and

wherein the buried strap region comprises dopants having the first doping polarity.