Clock controller with clock source fail-safe logic
DCFirst Claim
1. A method comprising:
- (a) detecting whether a first clock signal is inadequate, wherein the first clock signal is generated by a first clock circuit;
(b) decoupling the first clock circuit from a system clock input lead of a processor after the detecting in (a), wherein the decoupling is not performed as a result of a signal from the processor;
(c) coupling a second clock circuit to the system clock input lead of the processor after the decoupling in (b);
(d) enabling a third clock circuit after the coupling in (c);
(e) decoupling the second clock circuit from the system clock input lead of the processor after the enabling in (d); and
(f) coupling the third clock circuit to the system clock input lead of the processor after the decoupling in (e).
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Abstract
A microcontroller integrated circuit with a clock controller and a processor automatically switches the source of the clock signal that clocks the processor from a failed fast external precision oscillator to a slow internal backup oscillator, then enables a fast internal precision oscillator, and finally switches to the fast internal precision oscillator. A failure detection circuit within the clock controller detects a failure of the external precision oscillator and sends an associated interrupt signal to the processor. The clock controller decouples the external oscillator from the processor and couples the backup oscillator to the processor. The microcontroller integrated circuit then enables the fast internal precision oscillator, decouples the backup oscillator, and couples the fast internal precision oscillator to the processor. The microcontroller integrated circuit conserves power by powering up the fast internal precision oscillator only after the external clock source has failed and by then disabling the failure detection circuit.
53 Citations
21 Claims
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1. A method comprising:
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(a) detecting whether a first clock signal is inadequate, wherein the first clock signal is generated by a first clock circuit; (b) decoupling the first clock circuit from a system clock input lead of a processor after the detecting in (a), wherein the decoupling is not performed as a result of a signal from the processor; (c) coupling a second clock circuit to the system clock input lead of the processor after the decoupling in (b); (d) enabling a third clock circuit after the coupling in (c); (e) decoupling the second clock circuit from the system clock input lead of the processor after the enabling in (d); and (f) coupling the third clock circuit to the system clock input lead of the processor after the decoupling in (e). - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 20, 21)
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11. An integrated circuit, comprising:
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(a) a processor with a system clock input lead; (b) a terminal, the terminal coupled to a first clock circuit, the first clock circuit generating a first clock signal; (c) a second clock circuit; (d) a third clock circuit; and (e) a clock controller coupled to the system clock input lead, wherein the clock controller is adapted to decouple the system clock input lead from the terminal and to couple the system clock input lead to the second clock circuit upon detecting that the first clock signal has failed, and wherein the clock controller is further adapted to turn on the third clock circuit upon detecting that the first clock signal has failed and wherein the clock controller decouples the system clock input lead from the second clock circuit and couples the system clock input lead to the third clock circuit. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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18. A microcontroller integrated circuit operable with an external first clock circuit, the microcontroller integrated circuit comprising:
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(a) a processor having a system clock input lead; (b) a terminal for receiving a first clock signal generated by the external first clock circuit; (c) a second clock circuit; (d) means for detecting whether the first clock signal is inadequate and, upon detecting that the first clock signal is inadequate, for decoupling the terminal from the system clock input lead and coupling the second clock circuit to the system clock input lead, wherein the means decouples the terminal from the system clock input lead and couples the second clock circuit to the system clock input lead without receiving any signal from the processor; and (e) a third clock circuit, wherein the means turns on the third clock circuit upon detecting that the first clock signal is inadequate and wherein the means couples the system clock input lead to ground after decoupling the terminal from the system clock input lead and before coupling the second clock circuit to the system clock input lead. - View Dependent Claims (19)
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Specification