Clock controller with clock source fail-safe logic

  • US 7,296,170 B1
  • Filed: 01/23/2004
  • Issued: 11/13/2007
  • Est. Priority Date: 01/23/2004
  • Status: Expired due to Fees
First Claim
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1. A method comprising:

  • (a) detecting whether a first clock signal is inadequate, wherein the first clock signal is generated by a first clock circuit;

    (b) decoupling the first clock circuit from a system clock input lead of a processor after the detecting in (a), wherein the decoupling is not performed as a result of a signal from the processor;

    (c) coupling a second clock circuit to the system clock input lead of the processor after the decoupling in (b);

    (d) enabling a third clock circuit after the coupling in (c);

    (e) decoupling the second clock circuit from the system clock input lead of the processor after the enabling in (d); and

    (f) coupling the third clock circuit to the system clock input lead of the processor after the decoupling in (e).

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