Synchronous data serialization circuit

• US 7,298,301 B2
• Filed: 08/16/2004
• Issued: 11/20/2007
• Est. Priority Date: 07/19/2001
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Zhang, Bo
• Primary Examiner(s): Williams; Howard L.
• Assistant Examiner(s): LAUTURE, JOSEPH J
• Application Number:
  US10/919,093
• Publication Number:
  US 20050015638A1
• Time in Patent Office: 1,191 Days
• Field of Search: 341/100, 341/101
• US Class Current: 341/101
• CPC Class Codes: H03K 17/04106 in field-effect transistor switches H03K17/0412, H03K17/0416 take precedence
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00
• CPC Class Codes: H03K 2005/00208 using differential stages
• CPC Class Codes: H03K 3/356043 with synchronous operation
• CPC Class Codes: H03K 3/356139 with synchronous operation
• CPC Class Codes: H03K 3/3562 of the master-slave type
• CPC Class Codes: H03M 9/00 Parallel/series conversion or vice versa digital stores in which the information is moved stepwise per se G11C19/00
• CPC Class Codes: H04J 3/047 Distributors with transistors or integrated circuits

Abstract

In accordance with the present invention a data processing circuit includes a first data path for processing first data. The first data path includes a first data storage circuit. A second data path is provided for processing second data. The second data path includes a second data storage circuit. A multiplexer having a first input coupled to the first data path and a second input coupled to the second data path receives the stored values. The multiplexer includes a select input coupled to a clock signal. A delay circuit is configured to delay storage of the second data in the second data storage circuit, wherein the first data storage circuit stores the first data in response to receiving a first timing signal, and the second data storage circuit stores the second data in response to receiving a second timing signal.

Claims

1. A transceiver for use between interconnected high speed fiber optic communication channels, the transceiver comprising:

an optical input system having a photo detect and driver circuit which is configured to receive an input signal from an input fiber optic channel and is configured to convert the input signal to packets of data;

a clock data recovery circuit coupled to the optical input system which is configured to receive packets of data from the optical input system and is configured to recover clock and data signals having a first frequency from the packets of data;

a demultiplexer coupled to the clock data recovery circuit which is configured to deserialize clock and data signals received from the clock data recovery circuit into a plurality of parallel signals having a second frequency lower than the first frequency;

an application specific integrated circuit coupled to the demultiplexer which is configured to perform at least one of monitoring and error correction functions at the second frequency on the plurality of parallel signals received from the demultiplexer;

a multiplexer and clock multiplication unit coupled to the application specific integrated circuit which is configured to convert the plurality of parallel signals received from the application specific integrated circuit into a signal bit stream at the first frequency, wherein the multiplexer is configured to operate to establish a phase relationship between each of the plurality of parallel signals received from the application specific integrated circuit and convert the parallel signals to a serial bit stream at the first frequency based upon the established phase relationship; and

an optical output system coupled to the multiplexer and clock multiplication unit which is configured to retransmit the single bit stream received from the multiplexer and clock multiplication unit onto an output fiber optic channel.

2. The transceiver of claim 1, wherein a laser driver is configured to retransmit the single bit stream received from the multiplexer and clock multiplication unit onto the output fiber optical channel.

3. The transceiver of claim 1, wherein the demultiplexer is configured to deserialize clock and data signals received from the clock data recovery circuit into sixteen parallel signals having a second frequency.

4. The transceiver of claim 1, wherein the optical input system, clock data recovery circuit, demultiplexer, application specific integrated circuit, multiplexer and clock multiplication unit, and optical output system are fabricated on a single silicon die.

5. The transceiver of claim 1, wherein the transceiver is implemented using current-controlled complementary metal-oxide semiconductor (C³MOS) logic.

6. The transceiver of claim 1, wherein the clock data recovery circuit comprises one or more D type flip-flops.

7. the transceiver of claim 6, wherein the clock data recovery circuit is configured to recover a data signal from the packets of data using a rising edge triggered D type flip-flop.

8. The transceiver of claim 6, wherein the clock data recovery circuit recovers a clock signal from the packets of data using a falling edge triggered D type flip-flop.

9. The transceiver of claim 8, further comprising a data signal circuit coupled to an input of the falling edge triggered D type flip-flop for delaying application of a signal to the falling edge triggered D type flip-flop.

10. The transceiver of claim 6, further comprising a clock delay circuit coupled to the multiplexer for delaying application of a clock signal to the multiplexer to compensate for delays introduced by the clock data recovery circuit.

11. The transceiver according to claim 1, wherein the multiplexer is operably connected to:

a plurality of data storage circuits, each of the data storage circuits configured to receive a respective parallel signal of the plurality of parallel signals and configured to store a data bi corresponding to the respective parallel signal at a time that is determined based on a received timing signal; and

a delay circuit, the delay circuit configured to cause a delay in the storage of a data bit in at least one of the data storage circuits.

12. A delay circuit comprising:

a first differentially connected MOS transistor;

a second differentially connected MOS transistor;

a first load resistor serially connected to a first inductor to form a first resistor-inductor pair;

a second load resistor serially connected to a second inductor to form a second resistor-inductor pair,

wherein the first resistor-inductor pair is coupled between a power supply line and the drain of the first differentially connected MOS transistor and the second resistor-inductor pair is coupled between a power supply line and the drain of the second differentially connected MOS transistor,

wherein the source of the first differentially connected MOS transistor and the second differentially connected MOS transistor are coupled together through a current source to a ground,

wherein a first input signal is received at a first input of the first differentially connected MOS transistor on a first differential data line, and a second input signal is received at a second input of the second differentially connected MOS transistor on a second differential data line,

wherein a first output is provided at a drain of the first differentially connected MOS transistor, and a second output is provided at a drain of the second differentially connected MOS transistor, and

wherein data may be either transmitted or received on the first differential data line and the second differential data line,

further comprising a first parallel combination of switched capacitors connected between the first output and ground, and a second parallel combination of switched capacitors connected between the second output and ground.

13. A delay circuit comprising:

a first differentially connected MOS transistor;

a second differentially connected MOS transistor;

a first load resistor serially connected to a first inductor to form a first resistor-inductor pair;

a second load resistor serially connected to a second inductor to form a second resistor-inductor pair,

wherein the first resistor-inductor pair is coupled between a power supply line and the drain of the first differentially connected MOS transistor and the second resistor-inductor pair is coupled between a power supply line and the drain of the second differentially connected MOS transistor,

wherein the source of the first differentially connected MOS transistor and the second differentially connected MOS transistor are coupled together through a current source to a ground,

wherein a first input signal is received at a first input of the first differentially connected MOS transistor on a first differential data line, and a second input signal is received at a second input of the second differentially connected MOS transistor on a second differential data line,

wherein a first output is provided at a drain of the first differentially connected MOS transistor, and a second output is provided at a drain of the second differentially connected MOS transistor, and

wherein data may be either transmitted or received on the first differential data line and the second differential data line,

further comprising a first parallel combination of switched capacitors connected between the first output and ground, and a second parallel combination of switched capacitors connected between the second output and ground, wherein the first parallel combination and second parallel combination of switched capacitors are selectively activated to vary delay times of the delay circuit.

14. A method of processing a signal between interconnected high speed fiber optic communication channels, the method comprising:

receiving an input signal from a fiber optic input channel and converting the input signal to packets of data;

recovering clock and data signals having a first frequency from the packets of data;

deserializing the clock and data signals into a plurality of parallel signals having a second frequency lower than the first frequency;

performing monitoring and error correction functions at the second frequency on the plurality of parallel signals;

establishing a phase relationship between each of the plurality of parallel signals;

multiplexing the plurality of parallel signals into a serial bit stream at the first frequency based upon the established phase relationship, and

retransmitting the serial bit stream received from the multiplexer and clock multiplication unit onto a fiber optic output channel.

15. The method of claim 14, wherein the clock and data signals are recovered from the packets of data using D type flip-flops.

16. The method of claim 14, wherein the data signal is recovered from the packets of data using a rising edge triggered D type flip-flop.

17. The method of claim 14, wherein the clock signal is recovered from the packets of data using a falling edge triggered D type flip-flop.

18. The method of claim 17, further comprising delaying application of a signal to the falling edge triggered D type flip-flop.

19. The method of claim 14, further comprising delaying deserializing the clock and data signals to compensate for delays caused by recovery of the clock and data signals.

20. The method according to claim 14, wherein the establishing the phase relationship further comprises:

storing a data bit corresponding to each of the respective parallel signals in a corresponding data storage circuit; and

delaying the storage of at least one of the stored data bits in its corresponding data storage circuit.