Digital PWM controller for preventing limit cycle oscillations
First Claim
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1. A method for minimizing limit cycle oscillations from an output of a switched power supply including a digital control loop having a digital pulse width modulator therein with a digital control input, comprising the steps of:
- combining a digital dither signal with a digital output of a digital proportional integral derivative engine in the digital control loop to provide a combined signal to drive the digital control input of the digital pulse width modulator, the digital dither signal comprising a noise signal; and
generating an output signal from the switched power supply based upon the combined signal, wherein limit cycle oscillations in the output signal appear as random noise in the output signal due to the digital dither signal.
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Abstract
An apparatus and method for minimizing limit cycle oscillations within a switched power supply includes providing a programmable dither signal as an input to the digital control loop connected between an output and a control input of the switched power supply. The dither signal minimizes limit cycle oscillations from the output of the switched power supply.
21 Citations
25 Claims
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1. A method for minimizing limit cycle oscillations from an output of a switched power supply including a digital control loop having a digital pulse width modulator therein with a digital control input, comprising the steps of:
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combining a digital dither signal with a digital output of a digital proportional integral derivative engine in the digital control loop to provide a combined signal to drive the digital control input of the digital pulse width modulator, the digital dither signal comprising a noise signal; and generating an output signal from the switched power supply based upon the combined signal, wherein limit cycle oscillations in the output signal appear as random noise in the output signal due to the digital dither signal. - View Dependent Claims (2, 3, 4, 5)
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6. A method for minimizing limit cycle oscillations from an output of a switched power supply including a digital control loop having a digital pulse width modulator therein, comprising the steps of:
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combining a dither signal with an output of a proportional integral derivative engine in the digital control loop to provide a combined signal; generating an output signal with minimized limit cycle oscillations from the switched power supply based upon the combined signal; and programmably selecting a resolution of an LSB of a programmable analog to digital converter in the digital control loop, wherein the programmably selected resolution of the LSB is greater than a LSB resolution of the digital pulse width modulator. - View Dependent Claims (7)
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8. A method for minimizing limit cycle oscillations from an output of a switched power supply including a digital control loop having a digital pulse width modulator therein, comprising the steps of:
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programmably selecting a resolution of an LSB of a programmable analog to digital converter in the digital control loop, wherein the programmably selected resolution of the LSB is greater than a LSB resolution of the digital pulse width modulator; combining a dither signal with the output of a proportional integral derivative engine in the digital control loop to provide a combined signal; and generating the output signal with minimized limit cycle oscillations from the switched power supply based upon the combined signal and the programmably selected LSB resolution of the analog to digital converter. - View Dependent Claims (9, 10, 11)
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12. An apparatus, comprising:
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a switched power supply having an input, an output and a control input; a digital control loop connected between the output and the control input, the digital control loop having an analog input and a digital input; and a digital input to the digital control loop for receiving a digital dither signal, the digital dither signal comprising a noise signal for causing limit cycle oscillations to appear as random noise in an output signal of the switched power supply. - View Dependent Claims (13, 14, 15, 16)
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17. An apparatus, comprising:
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a switched power supply having an input, an output and a control input; a digital control loop connected between the output and the control input; and an input to the digital control loop for a dither signal, the dither signal comprising a noise signal causing limit cycle oscillations to appear as random noise in an output signal of the switched power supply, wherein the digital control loop further comprises; an analog to digital converter connected to the output of the switched power supply; a proportional integral derivative engine connected to the analog to digital converter; an adder circuit connected to an output of the proportional integral derivative engine and the input to the digital control loop for combining the dither signal with the output of the proportional integral derivative engine to provide a combined signal that causes limit cycle oscillations to appear as random noise in the output signal; and a digital pulse width modulator for generating the output signal to control the switched power supply. - View Dependent Claims (18, 19, 20)
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21. A digital control loop for a switched power supply, comprising:
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an analog to digital converter connected to an output of the switched power supply; a proportional integral derivative engine connected to the analog to digital converter; an input to the digital control loop for a dither signal, the dither signal comprising a noise signal for causing limit cycle oscillations to appear as random noise in an output signal of the switched power supply; an adder circuit connected to an output of the proportional integral derivative engine and to the input to the control loop for combining the dither signal with the output of the proportional integral derivative engine in the digital control loop to provide a combined signal; and a digital pulse width modulator for generating the output signal for controlling the switched power supply based upon the combined signal. - View Dependent Claims (22, 23, 24, 25)
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Specification