Multistage digital cross connect with synchronized configuration switching

• US 7,301,941 B2
• Filed: 01/16/2001
• Issued: 11/27/2007
• Est. Priority Date: 04/11/2000
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Dally, William J.
• Primary Examiner(s): Chan; Wing
• Assistant Examiner(s): Sefcheck; Gregory B.
• Application Number:
  US09/761,538
• Publication Number:
  US 20010053160A1
• Time in Patent Office: 2,506 Days
• Field of Search: 370/385, 370/387, 370/388, 370/370, 370/371, 370/376, 370/378, 370/379, 370/369, 370/375, 370/503, 370/373, 370/374
• US Class Current: 370/374
• CPC Class Codes: H04J 2203/0003 Switching fabrics, e.g. transport network, control network
• CPC Class Codes: H04Q 11/0478 Provisions for broadband connections
• CPC Class Codes: H04Q 11/06 Time-space-time switching
• CPC Class Codes: H04Q 2213/1302 Relay switches
• CPC Class Codes: H04Q 2213/1304 Coordinate switches, crossbar, 4/2 with relays, coupling field
• CPC Class Codes: H04Q 2213/13076 Distributing frame, MDF, cross-connect switch
• CPC Class Codes: H04Q 2213/13103 Memory
• CPC Class Codes: H04Q 2213/13292 Time division multiplexing, TDM
• CPC Class Codes: H04Q 2213/13305 Transistors, semiconductors in general
• CPC Class Codes: H04Q 2213/1334 Configuration within the switch
• CPC Class Codes: H04Q 2213/13367 Hierarchical multiplexing, add-drop multiplexing
• CPC Class Codes: H04Q 2213/13393 Time slot switching, T-stage, time slot interchanging, TSI
• CPC Class Codes: H04Q 3/68 Grouping or interlacing selector groups or stages

Abstract

A digital cross connect comprises plural switching stages. Each stage has plural switches which receive plural frames of time multiplexed input data and which switch the data in time and space. Configurations of the switches change in frame synchronization at the start of a synchronized data frame. Both the configuration data and a frame clock may be propagated through the plural stages from a master switch. First and last stages of the digital cross connect may be implemented on common chips having two framing time bases. Data may be aligned to a global frame clock and interchanged using a single random access memory in a time slot interchanger. The write address to the random access memory is generated from a local frame counter keyed to the input data frame while a read address is transformed from a global frame counter.

Claims

1. A digital cross connect comprising:

plural switching stages, each stage having plural switches receiving plural frames of time multiplexed input data and switching the data in time and space; and

configuration storage at each switch configured to store a primary time/space configuration table and a standby time/space configuration table for the switch, all switches switching configuration between the primary time/space configuration and the standby time/space configuration in frame synchronization at the start of synchronized data frames by synchronizing switches of successive stages to a configuration select signal propagated from at least one switch of an input stage, wherein configuration switching is initiated by a prepare-to-switch signal propagated from a master switch to all switches of an output stage and the input stage, the at least one switch of the input stage then propagating the configuration select signal, and each switch is configured to switch between the primary time/space configuration table and the standby time/space configuration table in response to the configuration select signal.

2. The digital cross connect as claimed in claim 1, wherein the configuration select signal is embedded within a frame of data.

3. The digital cross connect as claimed in claim 2, wherein the configuration select signal is embedded in an Al byte of a SONET frame.

4. The digital cross connect as claimed in claim 3, wherein the configuration select signal is embedded in a fourth A1 byte of an STS-48 frame.

5. The digital cross connect as claimed in claim 1, wherein the prepare-to-switch signal is embedded within a frame of data.

6. The digital cross connect as claimed in claim 5, wherein the prepare-to-switch signal is embedded in an A1 byte of a SONET frame.

7. The digital cross connect as claimed in claim 6, wherein the prepare-to-switch signal is embedded in a second and a third bytes of an STS-48 frame.

8. The digital cross connect as claimed in claim 1, wherein switches of a first and a last of said plural switching stages are on common chips.

9. The digital cross connect as claimed in claim 8, wherein the common chips having the first and the last stages support respective framing time bases for the first and the last stages.

10. The digital cross connect as claimed in claim 8, wherein connections from the first stage expand in space from input connections, and connections to the last stage concentrate in space to output connections.

11. The digital cross connect as claimed in claim 10, wherein chips of a common design support the switches of all stages.

12. The digital cross connect as claimed in claim 1, wherein the prepare-to-switch signal from the master switch is in a signal which is qualified to distinguish the signal from the master switch from signals from other switches.

13. The digital cross connect as claimed in claim 12, wherein the qualifier and the configuration data are embedded in A1 bytes of a SONET frame.

14. The digital cross connect as claimed in claim 1, wherein the master switch is in a middle stage.

15. The digital cross connect as claimed in claim 1, wherein each switch comprises a time slot interchanger associated with each input and output port thereof and a space switch.

16. The digital cross connect as claimed in claim 1, wherein (i) switches of a last stage are configured to propagate the prepare-to-switch signal to corresponding switches of a first stage and (ii) the switches of the first stage are configured to propagate the configuration select signal in response to the prepare-to-switch signal.

17. The digital cross connect as claimed in claim 1, wherein the prepare-to-switch signal comprises (i) information indicating that the prepare-to-switch signal is present and (ii) information indicating which time/space configuration table to select upon receipt of the configuration select signal.

18. The digital cross connect as claimed in claim 1, wherein a new time/space configuration is loaded into the standby time/space configuration table prior to the master switch propagating the prepare-to-switch signal.

19. A method of cross connecting digital data comprising:

providing plural switching stages, each stage having plural switches receiving plural frames of time multiplexed input data and switching the data in time and in space;

providing configuration storage at each switch, wherein the configuration storage is configured to store a primary time/space configuration table and a standby time/space configuration table for the switch;

propagating a configuration select signal from at least one input switch of an input stage to successive stages; and

switching configuration of the switches in frame synchronization at the start of synchronized data frames by synchronizing switches of the successive stages to the configuration select signal, wherein configuration switching is initiated by a prepare-to-switch signal propagated from a master switch to all switches of an output stage and the input stage, the at least one switch of the input stage then propagating the configuration select signal, and each switch switching between the primary and standby tables in response to the configuration select signal.

20. The method as claimed in claim 19, wherein the configuration select signal is embedded within a frame of data.

21. The method as claimed in claim 20, wherein the configuration select signal is embedded in an A1 byte of a SONET frame.

22. The method as claimed in claim 21, wherein the configuration select signal is embedded in a fourth A1 byte of an STS-48 frame.

23. The method as claimed in claim 19, wherein the prepare-to-switch signal is embedded within a frame of data.

24. The method as claimed in claim 23, wherein the prepare-to-switch signal is embedded in an A1 byte of a SONET frame.

25. The method as claimed in claim 24, wherein the prepare-to-switch signal is embedded in a second and a third bytes of an STS-48 frame.

26. The method as claimed in claim 19, wherein switches of a first and a last of said plural switching stages are on common chips.

27. The method as claimed in claim 26, further comprising switching the data of the first and the last stages in synchronization with respective framing time bases for the first and the last stages.

28. The method as claimed in claim 26, wherein the frames from the first stage expand in space from input connections, and frames to the last stage concentrate in space to output connections.

29. The method as claimed in claim 28, wherein chips of a common design support the switches of all stages.

30. The method as claimed in claim 19, wherein the prepare-to-switch signal from the master switch is in a signal which is qualified to distinguish the master signal from signals from other switches.

31. The method as claimed in claim 30, wherein the qualifier and the configuration data are embedded in A1 bytes of a SONET frame.

32. The method as claimed in claim 19, wherein the master switch is in a middle stage.

33. The method as claimed in claim 19, wherein each switch comprises a time slot interchanger associated with each input and output port thereof and a space switch.

34. A digital cross connect comprising:

plural switching stages, each stage having plural switching means for receiving plural frames of time multiplexed input data and switching the data in time and space;

configuration storage means at each switching means for storing a primary time/space configuration table and a standby time/space configuration table for the switching means; and

means for switching configuration of the plural switching means in synchronization with a configuration select signal propagated from at least one input switching means of an input stage, wherein (i) configuration switching is initiated by a prepare-to-switch signal propagated from a master switch to all switching means of an output stage and the input stage, (ii) the at least one input switching means of the input stage then propagating the configuration select signal, and (iii) each of the plural switching means switching between the primary and standby tables in response to the configuration select signal.

35. A digital cross connect comprising:

plural switching stages, each stage having plural switches, each comprising a time slot interchanger associated with each input and output port thereof and a space switch, each switch receiving plural frames of time multiplexed input data and switching the data in time and space; and

configuration storage at each switch configured to store a primary time/space configuration table and a standby time/space configuration table for the switch, all switches switching configuration in frame synchronization at the start of synchronized data frames, wherein (i) configuration switching is initiated by a prepare-to-switch signal propagated from a master switch to all switches of an output stage and an input stage, (ii) at least one switch of the input stage then propagating the configuration select signal, and (iii) each switch switching between the primary table and the standby table in response to the configuration select signal.

36. A method of cross connecting digital data comprising:

providing plural switching stages, each stage having plural switches, each comprising a time slot interchanger associated with each input and output port thereof and a space switch, each switch receiving plural frames of time multiplexed input data and switching the data in time and in space;

providing configuration storage at each switch, wherein the configuration storage is configured to store a primary time/space configuration table and a standby time/space configuration table for the switch; and

switching configuration of the switches between the stored time/space configurations in frame synchronization at the start of synchronized data frames by synchronizing switches of the successive stages to the configuration select signal, wherein (i) configuration switching is initiated by a prepare-to-switch signal propagated from a master switch to all switches of an output stage and an input stage, (ii) at least one switch of the input stage then propagating the configuration select signal, and (iii) each switch switches between the primary table and the standby table in response to the configuration select signal.

37. A digital cross connect comprising:

plural switching stages, each stage having plural switching means, each comprising a time slot interchanger associated with each input and output port thereof and a space switch, for receiving plural frames of time multiplexed input data and switching the data in time and space;

configuration storage means at each switching means for storing a primary time/space configuration table and a standby time/space configuration table for the switching means; and

means for switching configuration of the plural switching means in frame synchronization at the start of synchronized data frames, wherein (i) configuration switching is initiated by a prepare-to-switch signal propagated from a master switch to all switches of an output stage and an input stage, (ii) at least one switching means of the input stage then propagating the configuration select signal, and (iii) each of the plural of switching means switching between the primary and the standby tables in response to the configuration select signal.

38. A digital cross connect comprising:

plural switching stages, each stage having plural switches on plural chips receiving plural frames of time multiplexed input data and switching the data in time and space, switches of different stages being on common chips supporting respective framing time bases for the different stages; and

configuration storage at each switch configured to store a primary time/space configuration table and a standby time/space configuration table, wherein each switch is configured to switch between the primary time/space configuration and standby time/space configuration in response to a configuration select signal.

39. The digital cross connect as claimed in claim 38, wherein connections from a first stage expand in space from input connections and connections to a second stage concentrate in space to output connections.

40. The digital cross connect as claimed in claim 38, wherein the different stages are first and final stages of the plural switching stages.

41. The digital cross connect as claimed in claim 40, wherein connections from the first stage expand in space from input connections, and connections to the final stage concentrate in space to output connections.

42. A switch circuit on an integrated circuit chip comprising:

switch circuitry receiving plural frames of time multiplexed input data and switching the data in time and space;

a first frame counter to which a first portion of the plural frames of time multiplexed input data is synchronized;

a second frame counter to which a second portion of the plural frames of time multiplexed input data is synchronized; and

configuration storage, wherein (i) the configuration storage is configured to store a primary time/space configuration and a standby time/space configuration and (ii) the switch circuitry is configured to switch between the primary time/space configuration and standby time/space configuration in response to a configuration select signal.

43. The switch circuit as claimed in claim 42, wherein connections expand in space from input connections to the first portion, and connections concentrate in space to output connections of the second portion.

44. The switch circuit as claimed in claim 42, wherein the switch circuitry responds to a prepare-to-switch signal received with the second portion to initiate the configuration select signal propagated with the first portion.

45. The switch circuit as claimed in claim 44, wherein the configuration select signal is embedded within a frame of data.

46. The switch circuit as claimed in claim 45, wherein the configuration select signal is embedded in an A1 byte of a SONET frame.

47. The switch circuit as claimed in claim 46, wherein the configuration select signal is embedded in a fourth A1 byte of an STS-48 frame.

48. The switch circuit as claimed in claim 45, wherein the prepare-to-switch signal is embedded within a frame of data.

49. The switch circuit as claimed in claim 48, wherein the configuration select signal and the prepare-to-switch signal are embedded within A1 bytes of a SONET frame.

50. The switch circuit as claimed in claim 44, wherein the prepare-to-switch signal is embedded within a frame of data.

51. The switch circuit as claimed in claim 50, wherein the prepare-to-switch signal is embedded in an A1 byte of a SONET frame.

52. The switch circuit as claimed in claim 51, wherein the prepare-to-switch signal is embedded in a second and a third bytes of an STS-48 frame.

53. The switch circuit as claimed in claim 42, wherein input frames to and output frames from the switch circuitry are programmably assignable to the first and second portions.