Capacitance sensor using relaxation oscillators

• US 7,307,485 B1
• Filed: 11/14/2005
• Issued: 12/11/2007
• Est. Priority Date: 11/14/2005
• Status: Expired due to Fees

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Snyder, Warren S., Ess, David Van
• Primary Examiner(s): Lee, Benny T.
• Assistant Examiner(s): Gannon, Levi
• Application Number:
  US11/273,708
• Time in Patent Office: 757 Days
• Field of Search: 331/150, 324/548, 324/658, 324/678
• US Class Current: 331/150
• CPC Class Codes: G01R 27/2605 Measuring capacitance capacitive sensors G01D5/24
• CPC Class Codes: H03K 3/0231 Astable circuits H03K3/0315 takes precedence
• CPC Class Codes: H03K 5/26 the characteristic being duration, interval, position, frequency, or sequence

Abstract

An apparatus that may be used to sense capacitance, as well as other functions. The apparatus includes a comparator circuit with hysteresis, a capacitor, and a current driver. The comparator circuit with hysteresis includes a first input and an output. The capacitor is coupled to the first input of the comparator circuit with hysteresis. The current driver is coupled to the output of the comparator circuit with hysteresis and to the capacitor. The current driver reciprocally sources and sinks a drive current through a terminal of the capacitor to oscillate a voltage potential at the terminal of the capacitor between a low reference potential and a high reference potential. The current driver is responsive to the output of the comparator circuit with hysteresis.

Claims

1. An apparatus, comprising:

a comparator circuit with hysteresis including a first input and an output;

a capacitor coupled to the first input of the comparator circuit with hysteresis;

a current driver coupled to the output of the comparator circuit with hysteresis and to the capacitor, the current driver to reciprocally source and sink a drive current through a terminal of the capacitor to oscillate a voltage potential at the terminal of the capacitor between a low reference potential and a high reference potential responsive to the output of the comparator circuit with hysteresis;

a processor coupled to execute instructions;

a current source to generate a first reference current; and

a scaler unit coupled to receive a digital current control signal from the processor and to selectively scale the first reference current in response to the digital current control signal to generate a second reference current to provide to the current driver.

2. The apparatus of claim 1, wherein a magnitude of the drive current is dependent upon the second reference current.

3. The apparatus of claim 1, wherein the comparator circuit with hysteresis comprises:

a flip-flop including first and second inputs and an output, the output of the flip-flop coupled to the current driver;

a first comparator including an output coupled to the first input of the flip-flop, a first input coupled to the capacitor, and a second input to receive the high reference potential; and

a second comparator including an output coupled to the second input of the flip-flop, a first input coupled to the first input of the first comparator, and a second input to receive the low reference potential.

4. The apparatus of claim 3, wherein the current driver includes:

a pull up path coupled between a first voltage rail and the terminal of the capacitor to source the drive current into the terminal of the capacitor, the pull up path responsive to the output of the flip-flop; and

a pull down path coupled between a second voltage rail and the terminal of the capacitor to sink the drive current from the terminal of the capacitor, the pull down path responsive to the output of the flip-flop.

5. The apparatus of claim 4, wherein the current driver further includes a current mirror circuit to mirror a reference current into the pull up and pull down paths.

6. The apparatus of claim 5,

wherein the pull up path includes first and second positive metal oxide semiconductor (“

PMOS”

) transistors coupled in series, a gate of the first PMOS transistor coupled to the output of the flip-flop,

wherein the pull down path includes first and second negative metal oxide semiconductor (“

NMOS”

) transistors coupled in series, a gate of the first NMOS transistor coupled to the output of the flip-flop,

wherein the mirror circuit includes a third PMOS transistor coupled between the first voltage rail and a reference current source, the third PMOS transistor having its gate and source coupled to a gate of the second PMOS transistor, and

wherein the mirror circuit includes a third NMOS transistor coupled between the second voltage rail and the reference current source, the third NMOS transistor having its gate and drain coupled to a gate of the second NMOS transistor.

7. A method to sense a capacitance, comprising:

charging and discharging a reference capacitor with a first drive current generated by a first oscillator oscillating at a first frequency;

charging and discharging a device under test (“

DUT”

) capacitor with a second drive current generated by a second oscillator oscillating at a second frequency, wherein the first and second drive currents are scaled from a common reference current; and

measuring a capacitance change across the DUT capacitor based on a relative change between the first and second frequencies.

8. The method of claim 7, further comprising:

generating a low voltage reference at which the first and second oscillators transition between discharging and charging the reference and DUT capacitors, respectively; and

generating a high voltage reference at which the first and second oscillators transition between charging and discharging, the reference and DUT capacitors, respectively.

9. The method of claim 8, further comprising:

generating a reference current; and

mirroring the reference current into the first and second oscillators to generate the first and second drive currents for charging and discharging the reference capacitor and the DUT capacitor, respectively.

10. The method of claim 8, wherein the low and high voltage references are selectable via a processor.

11. The method of claim 10, wherein the processor is clocked by the first oscillator at the first frequency.

12. The method of claim 8, further comprising:

generating a first reference current;

mirroring the first reference current into the first oscillator to generate the first drive current for charging and discharging the reference capacitor;

generating a second reference current;

mirroring the second reference current in the second oscillator to generate the second drive current for charging and discharging the DUT capacitor;

adjusting one of the first reference current or the second reference current until the first frequency of the first oscillator matches the second frequency of the second oscillator; and

computing the absolute capacitance of the DUT capacitor based at least in part on a current difference between the first and second reference currents when the first and second frequencies match.

13. The method of claim 7, wherein measuring the capacitance change across the DUT capacitor based on the relative change between the first and second frequencies includes:

generating a first clock pulse by the first oscillator;

dividing a second clock pulse generated by the second oscillator by N to generate N second clock pulses; and

counting the number of N second clock pulses that occur during a first clock pulse.

14. A capacitance sensor, comprising:

a first oscillator coupled to charge and discharge a reference capacitor with a first drive current at a first frequency, the first oscillator including;

a comparator circuit with hysteresis including a first input coupled to the reference capacitor and an output; and

a current driver coupled to the output of the comparator circuit with hysteresis and to the reference capacitor, the current driver to reciprocally source and sink the first drive current through a terminal of the reference capacitor to oscillate a voltage potential at the terminal of the reference capacitor between a low reference potential and high reference potential responsive to the output of the comparator circuit with hysteresis;

a second oscillator to charge and discharge a device under test (“

DUT”

) capacitor with a second drive current at a second frequency; and

a frequency comparator coupled to the first and second oscillators to output a signal indicative of a capacitance change across the DUT capacitor based on a frequency difference between the first and second frequencies.

15. The capacitance sensor of claim 14, further comprising:

a voltage source to generate a reference voltage;

a voltage scaler coupled to scale the reference voltage to generate a low voltage reference and a high voltage reference, the voltage scaler coupled to provide the low and high voltage references to the first and second oscillators, wherein the first and second oscillators are coupled to oscillate the reference capacitor and the DUT capacitor between the low and high voltage references;

a reference current source to generate a first reference current; and

a current scaler coupled to scale the first reference current to generate second and third reference currents, wherein the first and second oscillators mirror the second and third reference currents, respectively, to generate the first and second drive currents, respectively.

16. The capacitance sensor of claim 15, further comprising a processor coupled to execute instructions, the processor coupled to the voltage and current scalers to select scaling factors for generating the low and high voltage references and for generating the second and third reference currents.

17. The capacitance sensor of claim 16, wherein the first oscillator is further coupled to provide a clock signal having the first frequency to the processor.

18. The capacitance sensor of claim 14, wherein the frequency comparator includes:

a divider circuit coupled to receive a clock signal from the second oscillator having the second frequency and to divide the clock signal by 2^N to generate a divided clock signal; and

an N-bit register counter coupled to count a number pulses of the divided clock signal that occur during a single pulse of a reference clock signal generated by the first oscillator and having the first frequency.

19. The capacitance sensor of claim 14, wherein the comparator circuit with hysteresis comprises:

a flip-flop including first and second inputs and an output, the output of the flip-flop coupled to the current driver;

a first comparator including an output coupled to the first input of the flip-flop, a first input coupled to the capacitor, and a second input to receive the high reference potential; and

a second comparator including an output coupled to the second input of the flip-flop, a first input coupled to the first input of the first comparator, and a second input to receive the low reference potential.

20. The capacitance sensor of claim 14, wherein the first and second drive currents are each asymmetrical for charging and discharging.