Reducing the time to convert an analog input sample to a digital code in an analog to digital converter (ADC)

• US 7,310,058 B2
• Filed: 07/13/2005
• Issued: 12/18/2007
• Est. Priority Date: 07/13/2005
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Pentakota, Visvesvaraya A., Oswal, Sandeep, Sinha, Vikas Kumar, Udupa, Anand Hariraj, Agarwal, Nitin
• Primary Examiner(s): NGUYEN, LINH V
• Application Number:
  US11/160,859
• Publication Number:
  US 20070013569A1
• Time in Patent Office: 888 Days
• Field of Search: 341/118, 341/120, 341/122, 341/155, 341/161, 341/172
• US Class Current: 341/161
• CPC Class Codes: H03M 1/168 and delivering the same number of bits

Abstract

A stage of a pipeline ADC which uses separate pairs of sampling network and amplifier (in a sample and hold circuit (SHA)) to provide inputs to quantizer (which generates a sub-code) and a switched capacitor network (implementing a DAC, a subtractor and amplification). Due to the use of separate components/paths to provide the input signal, the throughput performance of the ADC is enhanced.

Claims

1. An analog to digital converter (ADC), comprising:

a first sampling circuit sampling an input signal;

a first amplifier receiving said sampled input signal from said first sampling circuit, and providing an amplified version of said sampled input signal as an output;

a quantizer sampling said output of said first amplifier for a first duration, and generating a sub-code representing a voltage of said input signal;

a second sampling circuit sampling said input signal;

a second amplifier receiving said sampled input signal from said second sampling circuit, and providing an amplified version of said sampled input signal as an output; and

a first circuit sampling said output of said second amplifier for a second duration, said first circuit generating an amplified residue signal for processing by a next stage also comprised in said ADC;

wherein said first duration is less than said second duration; and

wherein said quantizer determines said sub-code in a decision duration which overlaps with said second duration.

2. The ADC of claim 1, wherein said first circuit comprises a plurality of capacitors, a plurality of switches and an amplifier together sampling said input signal and amplifying a difference of said strength and a voltage equivalent of said sub-code to generate said amplified residue signal.