Non-volatile memory device having page buffer for verifying pre-erase

• US 7,313,024 B2
• Filed: 11/30/2005
• Issued: 12/25/2007
• Est. Priority Date: 03/15/2005
• Status: Expired due to Fees

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Lee, Ju Yeab
• Primary Examiner(s): Zarabian, Amir
• Assistant Examiner(s): Graham, Kretelia
• Application Number:
  US11/164,608
• Publication Number:
  US 20060291289A1
• Time in Patent Office: 755 Days
• Field of Search: 365/185.22, 365/185.29
• US Class Current: 365/185.22
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells

Abstract

Non-volatile memory devices have a page buffer that can verify pre-erase. A non-volatile memory device may include a cell array having a plurality of strings consisting of memory cells disposed at the intersection regions of bit lines and word lines, and a plurality of page buffers connected to the bit lines through a sensing line. Each of the plurality of page buffers may include a pre-erase detection unit that detects pre-erase in response to a signal of the sensing line in order to verify whether data programmed into the memory cells have been erased, a main erase detection unit that detects main erase in response to a signal of the sensing line in order to verify whether data programmed into the memory cells have been erased, a latch circuit which stores data in response to an output signal of the pre-erase detection unit at the time of pre-erase verify and stores data in response to an output signal of the main erase detection unit at the time of main erase verify, and a verify unit that verifies pass or fail of the pre-erase or main erase in response to a signal of the latch circuit at the time of pre-erase verify or main erase verify.

Claims

1. A non-volatile memory device, comprising:

a cell array having a plurality of strings consisting of memory cells coupled to bit lines and word lines; and

a plurality of page buffers connected to the bit lines through a sensing line,

each of the plurality of page buffers comprises;

a pre-erase detection unit that detects pre-erase in response to a signal of the sensing line and a pre-erase verify signal in order to verify whether data programmed into the memory cells have been erased;

a main erase detection unit that detects main erase in response to the signal of the sensing line in order to verify whether data programmed into the memory cells have been erased;

a latch circuit which stores data in response to an output signal of the pre-erase detection unit at the time of pre-erase verify and stores data in response to an output signal of the main erase detection unit at the time of main erase verify; and

a verify unit that verifies pass or fail of the pre-erase or main erase in response to a signal of the latch circuit at the time of pre-erase verify or main erase verify,

wherein the main erase detection unit initializes a first node of the latch circuit at the time of the pre-erase.

2. The non-volatile memory device as claimed in claim 1, wherein if the pre-erase verify is pass, the main erase is performed, and if the pre-erase verify is fail, the pre-erase is again performed.

3. The non-volatile memory device as claimed in claim 1, wherein the pre-erase detection unit is connected between a power supply voltage and the first node of the latch circuit, and controls the first node to have the power supply voltage when the pre-erase is successful.

4. The non-volatile memory device as claimed in claim 1, wherein the pre-erase detection unit includes a first PMOS transistor that is turned on according to the pre-erase verify signal that becomes logic low only at the tune of the pre-erase verify, and a second PMOS transistor that is turned on when the signal of the sensing line becomes logic low at the time of the pre-erase verify.

5. The non-volatile memory device as claimed in claim 1, wherein a first node of the latch circuit becomes logic low and a second node thereof becomes logic high at the time of the pre-erase.

6. The non-volatile memory device as claimed in claim 1, wherein each of the plurality of page buffers further includes a reset unit that initializes the first node of the latch circuit to logic high and a second node thereof to logic low for the main erase verify.

7. The non-volatile memory device as claimed in claim 1, wherein each of the plurality of page buffers includes a precharge unit that precharges the sensing line in order to verify the pre-erase or main erase;

and

a bit line select and bias unit that selects one of the bit lines.