Power FET with embedded body pickup

• US 7,315,052 B2
• Filed: 03/02/2006
• Issued: 01/01/2008
• Est. Priority Date: 03/02/2006
• Status: Active Grant

• Current Assignee: Microchip Technology Incorporated
• Original Assignee: Micrel Incorporated (Microchip Technology Incorporated)
• Inventors: Alter, Martin
• Primary Examiner(s): Jackson; Jerome
• Assistant Examiner(s): Valentine; Jami M
• Application Number:
  US11/368,092
• Publication Number:
  US 20070205461A1
• Time in Patent Office: 670 Days
• Field of Search: 257/288, 257/343, 438/197
• US Class Current: 257/288
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A power transistor formed on a semiconductor substrate and including a lateral array of polysilicon lines separated by alternating source and drain regions includes one or more body contact diffusion regions formed in the source regions where each body contact diffusion region has a length that extends to the edges of the two adjacent polysilicon lines, and one or more body pickup contacts where each body pickup contact is formed over a respective body contact diffusion region. In one embodiment, the body contact diffusion regions are formed in a fabrication process using ion implantation of dopants of a first type through a body diffusion mask. Each body contact diffusion region defined by an exposed area in the body diffusion mask has a drawn area that overlaps the respective two adjacent polysilicon lines.

Claims

1. A power transistor formed on a semiconductor substrate and including a lateral array of polysilicon lines separated by alternating source and drain regions, the power transistor comprising:

one or more elongated body contact diffusion regions formed in areas of the source regions not receiving the source diffusion, each elongated body contact diffusion region having a rectangular shape with a width that extends in parallel with the edges of the two adjacent polysilicon lines and a length that extends perpendicular to the edges of the two adjacent polysilicon lines and having a dopant type opposite to the dopant type of the source region; and

one or more body pickup contacts, each body pickup contact formed only over a respective body contact diffusion region,

wherein the body contact diffusion regions are formed in a fabrication process using ion implantation of dopants of a first type through a body diffusion mask, each body contact diffusion region defined by an exposed area in the body diffusion mask having a drawn area that overlaps the respective two adjacent polysilicon lines.

2. The power transistor of claim 1, wherein the drawn area of the body contact diffusion region in the body diffusion mask overlaps each of the two adjacent polysilicon lines by about 30% of the length of the polysilicon lines.

3. The power transistor of claim 1, wherein the source and drain regions are formed in the fabrication process using ion implantation of a dopants of a second type, opposite to the first type, through a source/drain diffusion mask, the source/drain diffusion mask being an inverse of the body diffusion mask and including covered areas corresponding to the drawn areas of the body contact diffusion regions.

4. The power transistor of claim 3, wherein the power transistor comprises an N-channel power transistor and the body contact diffusion regions are formed using P-type dopants while the source and drain regions are formed using N-type dopants.

5. The power transistor of claim 3, wherein the power transistor comprises a P-channel power transistor and the body contact diffusion regions are formed using N-type dopants while the source and drain regions are formed using P-type dopants.

6. The power transistor of claim 1, further comprising:

one or more source contacts formed in the source regions, the source contacts being formed separate from the body pickup contacts; and

a metal line connecting the source contacts and the body pickup contacts formed in each source region.

7. The power transistor of claim 6, wherein in each source region, a body contact diffusion regions and a body pickup contact are included for every N numbers of source contacts.

8. The power transistor of claim 7, wherein N is 5 or greater.

9. The power transistor of claim 1, wherein the body contact diffusion regions each has a width that is at least the same as the size of the body pickup contact.

10. The power transistor of claim 9, wherein the body contact diffusion regions each has a width that is at least twice the size of the body pickup contact.