Power control system for synchronous memory device

• US 7,320,082 B2
• Filed: 12/18/2003
• Issued: 01/15/2008
• Est. Priority Date: 10/10/1997
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Barth, Richard M., Tsern, Ely K., Hampel, Craig E., Stark, Donald C.
• Primary Examiner(s): CHEUNG, MARY DA ZHI WANG
• Application Number:
  US10/742,327
• Publication Number:
  US 20040141404A1
• Time in Patent Office: 1,489 Days
• Field of Search: 713/300, 713/322, 713500-503, 713600-601, 712216-219, 710/1, 711 1- 6
• US Class Current: 713/500
• CPC Class Codes: G06F 1/3225 of memory devices
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 9/3869 Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A memory device with multiple clock domains. Separate clocks to different portions of the control circuitry create different clock domains. The different domains are sequentially turned on as needed to limit the power consumed. The turn on time of the domains is overlapped with the latency for the memory access to make the power control transparent to the user accessing the memory core. The memory device can dynamically switch between a fast and a slow clock depending upon the needed data bandwidth. The data bandwidth across the memory interface can be monitored by the memory controller, and when it drops below a certain threshold, a slower clock can be used. The clock speed can be dynamically increased as the bandwidth demand increases.

Claims

1. A memory device having a core that includes memory cells, the memory device comprising:

a clock receiver circuit to receive an external clock signal;

a delay locked loop circuit coupled to the clock receiver circuit, wherein;

during a standby power mode the delay locked loop circuit and the clock receiver circuit are turned on; and

during a second power mode, the delay locked loop circuit is turned off; and

an input to receive control information that specifies a transition from the standby power mode to an active mode, wherein a sense operation is performed during the active mode, and wherein a row of the memory cells is sensed during the sense operation.

2. The memory device of claim 1, wherein during the active mode, a clock signal output from the delay locked loop circuit is electrically coupled to sense control logic, and wherein a row command instructs the sense control logic to perform the sense operation.

3. The memory device of claim 1, further including a receiver circuit to receive data, wherein the receiver circuit is turned on after a delay time in response to receiving a write command, the receiver circuit to receive data to be written to the row of the memory cells.

4. The memory device of claim 3, further including a write control circuit, coupled to the receiver circuit, wherein a clock signal generated by the delay locked loop circuit is provided to the write control circuit in response to receiving the write command.

5. The memory device of claim 3, wherein the data to be written to the row of the memory cells is written to a location within the row, wherein the location is specified by a column address.

6. The memory device of claim 3, further including a register to program the delay time.

7. The memory device of claim 1, further including a read control circuit, coupled to the core, wherein the read control circuit is turned on in response to receiving a read command that specifies an access of data from the row of the memory cells.

8. The memory device of claim 7, wherein a clock signal generated by the delay locked loop circuit is provided to the read control circuit in response to receiving the read command.

9. A memory device comprising:

a memory core including memory cells;

a clock receiver circuit to receive an external clock signal;

a delay locked loop circuit coupled to the clock receiver circuit, wherein;

during a standby power mode the delay locked loop circuit and the clock receiver circuit are turned on; and

during a second power mode, the delay locked loop circuit is turned off;

an input to receive control information that specifies a transition from the standby power mode to an active mode, wherein the memory device performs a sense operation on a specified row of memory cells during the active mode;

a receiver circuit to receive data to be written to memory cells sensed during the sense operation, wherein the receiver circuit is turned on after a latency period in response to receiving a write command; and

a register to program the latency period.

10. The memory device of claim 9, wherein during the second power mode, the clock receiver circuit is turned off.

11. The memory device of claim 9, further including a first control line, coupled to the clock receiver circuit and the delay locked loop circuit, wherein, during the second power mode, the delay locked loop circuit and the clock receiver are turned off using the first control line.

12. The memory device of claim 9, wherein during a third power mode, the delay locked loop circuit is in a low power configuration and the clock receiver is turned on.

13. The memory device of claim 12, wherein a resynchronization time of the delay locked loop circuit, when in the low power configuration, is less than a resynchronization time of the delay locked loop circuit when in the second power mode.

14. A method of operation of a memory device having a core of memory cells, the method comprising:

receiving a command that specifies a power down mode;

turning off a delay locked loop circuit in response to the command that specifies the power down mode;

operating the memory device in a standby power mode, wherein the delay locked loop circuit is turned on in the standby mode;

transitioning from the standby power mode to an active mode; and

sensing a row of the memory cells during the active mode.

15. The method of claim 14, further including:

receiving a write command; and

in response to the write command, turning on a receiver circuit to receive data after a period of time transpires, wherein the data is written to the row of memory cells.

16. The method of claim 15, further including programming the period of time using a register.

17. The method of claim 14, further including:

receiving a read command; and

in response to the read command, turning on a read pipeline to output data from the memory device.

18. A memory device comprising:

a memory core including memory cells;

a delay locked loop circuit wherein;

during a standby power mode, the delay locked loop circuit is turned on; and

during a power down mode, the delay locked loop circuit is turned off;

an input to receive control information that specifies a transition from the standby power mode to an active mode, wherein the memory device performs a sense operation on a specified row of the memory cells during the active mode;

a clock receiver circuit, coupled to the delay locked loop circuit, to receive an external clock signal, wherein the clock receiver circuit is turned on during the standby power mode;

a first control line, coupled to the clock receiver circuit and the delay locked loop circuit, wherein, during the power down mode, the delay locked loop and the clock receiver are turned off using the first control line; and

a receiver circuit to receive data, after a latency period transpires, in response to receiving a write command, the data to be written to the row of the memory cells.

19. The memory device of claim 18, wherein during a nap power mode, the delay locked loop circuit is in a low power configuration and the clock receiver circuit is turned on.

20. The memory device of claim 19, wherein a resynchronization time of the delay locked loop circuit in the low power configuration is less than a resynchronization time of the delay locked loop circuit in the power down mode.

21. The memory device of claim 18, further including a register to program the latency period.

22. The memory device of claim 18, wherein the receiver circuit is turned on before the data arrives.

23. A memory device comprising:

a memory core including memory cells;

a delay locked loop circuit wherein;

during a nap power mode, the delay locked loop is in a low power configuration; and

during a standby power mode, the delay locked loop circuit is turned on;

a clock receiver circuit, coupled to the delay locked loop circuit, to receive an external clock signal, wherein the clock receiver circuit is turned on during both the standby power mode and the nap power mode;

an input to receive control information that specifies a transition from the standby power mode to an active mode, wherein the memory device performs a sense operation on a specified row of the memory cells during the active mode; and

a receiver circuit to receive data, after a latency period transpires, in response to receiving a write command, the data to be written to the row of the memory cells.

24. The memory device of claim 23, wherein during a power down mode, the delay locked loop circuit is turned off.

25. The memory device of claim 24, wherein a resynchronization time of the delay locked loop circuit when in the nap power configuration is less than a resynchronization time of the locked loop circuit when in the power down mode.

26. The memory device of claim 23, wherein the receiver circuit is turned on before the data arrives.

27. The memory device of claim 23, further including a register to program the latency period.

28. A memory device having a core that includes memory cells, the memory device comprising:

a clock receiver circuit to receive an external clock signal;

a delay locked loop circuit coupled to the clock receiver circuit, wherein;

during a first power mode the delay locked loop circuit and the clock receiver circuit are turned on; and

during a second power mode, the delay locked loop circuit is turned off; and

an input to receive control information that specifies a transition from the first power mode to an active mode, wherein power consumption in the first power mode is less than that consumed while in the active mode, wherein a sense operation is performed during the active mode, and wherein a row of the memory cells is sensed during the sense operation.

29. The memory device of claim 28, wherein during the active mode, a clock signal output from the delay locked loop circuit is electrically coupled to sense control logic, and wherein a row command instructs the sense control logic to perform the sense operation.

30. The memory device of claim 28, further including a receiver circuit to receive data, wherein the receiver circuit is turned on after a delay time in response to receiving a write command, the receiver circuit to receive data to be written to the row of the memory cells.

31. The memory device of claim 30, further including a write control circuit, coupled to the receiver circuit, wherein a clock signal generated by the delay locked loop circuit is provided to the write control circuit in response to receiving the write command.

32. The memory device of claim 30, wherein the data to be written to the row of the memory cells is written to a location within the row, wherein the location is specified by a column address.

33. The memory device of claim 30, further including a register to program the delay time.

34. The memory device of claim 28, further including a read control circuit, coupled to the core, wherein the read control circuit is turned on in response to receiving a read command that specifies an access of data from the row of the memory cells.

35. The memory device of claim 34, wherein a clock signal generated by the delay locked loop circuit is provided to the read control circuit in response to receiving the read command.