Network processor having cyclic redundancy check implemented in hardware

• US 7,320,102 B2
• Filed: 04/10/2006
• Issued: 01/15/2008
• Est. Priority Date: 09/19/2000
• Status: Expired due to Fees

• Current Assignee: TAG Foundation (SeeSaw Foundation)
• Original Assignee: BBN Technologies (Rtx Corporation)
• Inventors: Milliken, Walter C.
• Primary Examiner(s): CHUNG, PHUNG M
• Application Number:
  US11/402,188
• Publication Number:
  US 20060242493A1
• Time in Patent Office: 645 Days
• Field of Search: None
• US Class Current: 714/781
• CPC Class Codes: H03M 13/09 Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
• CPC Class Codes: H03M 13/6513 Support of multiple code types, e.g. unified decoder for LDPC and turbo codes
• CPC Class Codes: H04L 1/0043 Realisations of complexity reduction techniques, e.g. use of look-up tables
• CPC Class Codes: H04L 1/0061 Error detection codes
• CPC Class Codes: H04L 2001/0094 Bus
• CPC Class Codes: H04L 69/12 Protocol engines

Abstract

A network processor [200] performs Cyclic Redundancy Check (CRC) operations using specialized hardware circuits [308-308]. The network processor [200] includes a plurality of hardwired CRC polynomials that are used to implement the CRC operations. A CRC instruction selects which polynomial to use when performing the CRC operation.

Claims

1. A network processor comprising:

a bus in communication with a plurality of hardwired Cyclic Redundancy Check (CRC) circuits, each CRC circuit implementing a CRC polynomial for generating a CRC result; and

a switch for directing input data to at least one of the CRC circuits based on a CRC instruction; and

an error detection circuit electrically coupled to the bus for determining whether the input data includes an error based on the CRC result.

2. The network device of claim 1, further comprising:

an input register file connected to the switch, and in communication to input ports of a network device.

3. The network device of claim 1, further comprising:

output register files connected to the switch, the output register files receiving the CRC result generated by the CRC circuit to which the input data was directed.

4. The network device of claim 1, wherein the hardwired CRC polynomials include an eight-bit, a ten-bit, a sixteen-bit, and a thirty-two-bit polynomial.

5. The network device of claim 1, wherein the error detection circuit includes the plurality of CRC circuits.

6. The network device of claim 1, wherein the error detecting circuit is configured to compare a CRC result to zero to detect an error.

7. A network processor comprising:

a bus in communication with a plurality of preexisting Cyclic Redundancy Check (CRC) circuits,

a switch for directing input data to at least one of the CRC circuits based on a CRC instruction based upon an indication of a polynomial included in a CRC instruction; and

an error detecting circuit electrically connected to the bus for determining whether the input data includes an error based on a CRC result output by the at least one CRC circuit to which the input data was directed.

8. The network processor of claim 7, wherein the error detecting circuit includes the plurality of CRC circuits.

9. The network processor of claim 7, wherein the error detecting circuit is configured to compare a CRC result to zero to detect an error.