Network processor having cyclic redundancy check implemented in hardware

  • US 7,320,102 B2
  • Filed: 04/10/2006
  • Issued: 01/15/2008
  • Est. Priority Date: 09/19/2000
  • Status: Expired due to Fees
First Claim
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1. A network processor comprising:

  • a bus in communication with a plurality of hardwired Cyclic Redundancy Check (CRC) circuits, each CRC circuit implementing a CRC polynomial for generating a CRC result; and

    a switch for directing input data to at least one of the CRC circuits based on a CRC instruction; and

    an error detection circuit electrically coupled to the bus for determining whether the input data includes an error based on the CRC result.

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