Storage device using interleaved memories to control power consumption

• US 7,325,104 B2
• Filed: 01/11/2006
• Issued: 01/29/2008
• Est. Priority Date: 01/11/2005
• Status: Expired due to Fees

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Satori, Kenichi, Konno, Tamaki, Aoki, Yoshitaka, Tsutsui, Keiichi, Nakanishi, Kenichi, Okubo, Hideaki, Bando, Hideaki
• Primary Examiner(s): Kim; Matthew
• Assistant Examiner(s): PATEL, HETUL B
• Application Number:
  US11/329,843
• Publication Number:
  US 20060184758A1
• Time in Patent Office: 748 Days
• Field of Search: 711/150, 711167-168, 711/169, 345533-535
• US Class Current: 711/150
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

A storage device includes a plurality of memories storing data; and a controller controlling the memories, the controller performing in parallel in a number of the memories, the number being specified by a supplied specifying signal, one of a data writing process for writing data supplied from a connection destination device to which the storage device is connectable and a data reading process for reading data requested by the connection destination device.

Claims

1. A storage device, comprising:

a plurality of memory means for storing data;

control means for controlling a number of the plurality of memory means in parallel to perform one of a data writing process for writing data supplied from a connection destination device to which the storage device is connected and a data reading process for reading data requested by the connection destination device; and

a grade register for storing a grade value for use by the control means in determining a data transfer rate for reading data from and writing data to the storage device by specifying the number of memory means to be used in parallel to store the data, and thereby determining a power consumption of the storage device.

2. The storage device as claimed in claim 1, further comprising data communication means for performing data communication with the connection destination device based on a PCI Express system.

3. A storage device, comprising:

a plurality of memory means for storing data; and

control means for controlling the memory means; and

a grade register for storing a grade value for use by the control means in determining a data transfer rate for reading data from and writing data to the storage device by specifying a number of the plurality of memory means to be interleaved in storing the data, and thereby determining a power consumption of the storage device;

wherein one of a minimum write speed of a data write process for writing data supplied from a connection destination device to which the storage device is connected and a minimum read speed of a data read process for reading data requested by the connection destination device is guaranteed.

4. A storage device, comprising:

a plurality of memories for storing data;

a controller for controlling a number of the plurality of memories in parallel, to perform one of a data writing process for writing data supplied from a connection destination device to which the storage device is connected and a data reading process for reading data requested by the connection destination device; and

a grade register for storing a grade value for use by the controller in determining a data transfer rate for reading data from and writing data to the storage device by specifying the number of memories to be used in parallel to store the data, thereby determining a power consumption of the storage device.

5. A storage device, comprising:

a plurality of memories for storing data;

a controller for controlling the memories; and

a grade register for storing a grade value for use by the controller in determining a data transfer rate for reading data from and writing data to the storage device by specifying a number of the plurality of memories to be interleaved in storing the data, thereby determining a power consumption of the storage device;

wherein one of a minimum write speed of a data write process for writing data supplied from a connection destination device to which the storage device is connected and a minimum read speed of a data read process for reading data requested by the connection destination device is guaranteed.

6. An information processing device, comprising:

a plurality of memory means for storing data;

control means for controlling a number of the plurality of memory means in parallel to perform one of a data writing process for writing data supplied from a connection destination device to which the information processing device is connected and a data reading process for reading data requested by the connection destination device; and

a grade register for storing a grade value for use by the control means in determining a data transfer rate for reading data from and writing data to the information processing device by specifying the number of memory means to be used in parallel to store the data, and thereby determining a power consumption of the information processing device.

7. An information processing device, comprising:

a plurality of memory means for storing data; and

control means for controlling the memory means; and

a grade register for storing a grade value for use by the control means in determining a data transfer rate for reading data from and writing data to the information processing device by specifying a number of the plurality of memory means to be interleaved in storing the data, and thereby determining a power consumption of the information processing device;

wherein one of a minimum write speed of a data write process for writing data supplied from a connection destination device to which the storage device is connected and a minimum read speed of a data read process for reading data requested by the connection destination device is guaranteed.

8. An information processing device, comprising:

a plurality of memories for storing data;

a controller for controlling a number of the plurality of memories in parallel, to perform one of a data writing process for writing data supplied from a connection destination device to which the information processing device is connected and a data reading process for reading data requested by the connection destination device; and

a grade register for storing a grade value for use by the controller in determining a data transfer rate for reading data from and writing data to the information processing device by specifying the number of memories to be used in parallel to store the data, thereby determining a power consumption of the information processing device.

9. An information processing device, comprising:

a plurality of memories for storing data;

a controller for controlling the memories; and

a grade register for storing a grade value for use by the controller in determining a data transfer rate for reading data from and writing data to the information processing device by specifying a number of the plurality of memories to be interleaved in storing the data, thereby determining a power consumption of the information processing device;

wherein one of a minimum write speed of a data write process for writing data supplied from a connection destination device to which the information processing device is connected and a minimum read speed of a data read process for reading data requested by the connection destination device is guaranteed.