Memory system having delayed write timing

• US 7,330,953 B2
• Filed: 03/27/2007
• Issued: 02/12/2008
• Est. Priority Date: 10/10/1997
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Barth, Richard M., Nguyen, David, Hampel, Craig E., Stark, Donald C., Ware, Frederick A., Davis, Paul G., Abhyankar, Abhijit M., Gasbarro, James A.
• Primary Examiner(s): BATAILLE, PIERRE MICHE
• Application Number:
  US11/692,162
• Publication Number:
  US 20070198868A1
• Time in Patent Office: 322 Days
• Field of Search: 711/167, 711/169, 711/168, 711/105, 711/106, 711/5, 711/100, 711/154, 365/189, 365/190, 365/222, 365/233, 365/230.03, 365/189.01, 370/375
• US Class Current: 711/167
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40611 External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/2218 Late write
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

A memory system has first, second and third interconnects and an integrated circuit memory device coupled to the interconnects. The second interconnect conveys a write command and a read command. The third interconnect conveys write data and read data. The integrated circuit memory device includes a pin coupled to the first interconnect to receive a clock signal. The memory device also includes a first plurality of pins coupled to the second interconnect to receive the write command and read command, and a second plurality of pins coupled to the third interconnect to receive write data and to assert read data. Control information is applied to initiate the write operation after a first predetermined delay time transpires from when the write command is received. During a clock cycle of the clock signal, two bits of read data are conveyed by each pin of the second plurality of pins.

Claims

1. A system comprising:

a first set of interconnect resources to convey;

a sense command; and

after the sense command, a write command that specifies a write operation;

a second set of interconnect resources to convey;

a row address that identifies row of a memory array to sense in response to the sense command; and

after the row address, a column address that identifies a column location of the row;

a third set of interconnect resources to convey data; and

a memory device comprising;

a memory core including a plurality of memory cells;

a first set of pins coupled to the first set of interconnect resources, the first set of pins to receive the sense command and the write command, wherein, after a first delay time transpires from when the write command is received at the first set of pins, the memory device applies a control signal to convey a plurality of data bits to the column location, in response to the write command;

a second set of pins coupled to the second set of interconnect resources, the second set of pins to receive the row address and the column address; and

a third set of pins coupled to the third set of interconnect resources, the third set of pins to receive the plurality of data bits after a second delay time has transpired from when the write command is received at the second set of pins.

2. The system of claim 1, wherein:

the first set of pins receives a read command; and

the third set of pins output read data to the third set of interconnect resources in response to the read command, wherein the read data is output after a third delay time has transpired from when the read command is received by the first set of pins, wherein the second delay time is based on the third delay time.

3. The system of claim 2, wherein the second delay time is based on the third delay time such that the second delay time is a channel turnaround time less than the third delay time.

4. The system of claim 2, wherein the memory device further comprises a pin to receive a clock signal, wherein, in response to the read command, each pin of the third set of pins outputs a first bit of the read data at a rising edge of the clock signal and a second bit of the read data at a falling edge of the clock signal.

5. The system of claim 2, wherein the memory device further comprises a pin to receive a clock signal, wherein, in response to the write command, each pin of the third set of pins receives two data bits of the plurality of data bits during a clock cycle of the clock signal.

6. A system comprising:

a first interconnect to convey a clock signal;

a second interconnect to convey;

a write command that specifies storage of write data in a memory core during a write operation; and

a read command that specifies output of read data accessed from the memory core;

a third interconnect to convey the write data and the read data; and

an integrated circuit memory device comprising;

a pin coupled to the first interconnect, the pin to receive the clock signal from the first interconnect;

a first plurality of pins coupled to the second interconnect, the first plurality of pins to receive the write command from the second interconnect, wherein, in response to the write command a write operation is initiated in the integrated circuit memory device after a first predetermined delay time transpires from when the write command is received at the first plurality of pins; and

a second plurality of pins coupled to the third interconnect, the second plurality of pins to receive the write data after a second predetermined delay time has transpired from when the write command is received at the first plurality of pins, and wherein, in response to the read command, each pin of the second plurality of pins conveys to the third interconnect, a first bit of the read data at a rising edge of the clock signal, and a second bit of the read data at a falling edge of the clock signal.

7. The system of claim 6, wherein:

the second interconnect conveys an activate command;

the first plurality of pins receives the activate command; and

wherein the integrated circuit memory device further comprises;

a memory core including a plurality of memory cells; and

a third plurality of pins to receive a row address, a first column address and a second column address, wherein;

the row address identifies a row of memory cells of the plurality of memory cells;

the activate command specifies that the memory device sense the row of memory cells identified by the row address;

the first column address identifies a column location at which to store the write data; and

the second column address identifies a column location at which to obtain the read data.

8. The system of claim 7, wherein

the first plurality of pins receives the activate command during a first command cycle, the write command during a second command cycle and the read command during a third command cycle;

and

the third plurality of pins receives the row address during the first command cycle, the first column address during the second command cycle, and the third column address during the third command cycle.

9. The system of claim 6, wherein control information is applied to initiate the write operation after the first predetermined delay time transpires from when the write command is received at the first plurality of pins.

10. A system comprising:

a first interconnect to convey a clock signal;

a second interconnect to convey;

a write command that specifies storage of write data in a memory core during a write operation; and

a read command that specifies output of read data accessed from the memory core;

a third interconnect to convey the write data and the read data; and

an integrated circuit memory device comprising;

a pin coupled to the first interconnect, the pin to receive the clock signal from the first interconnect;

a first set of pins coupled to the second interconnect, the first set of pins to receive the write command and the read command from the second interconnect, wherein, in response to the write command, the integrated circuit memory device applies control information to initiate the write operation, wherein the control information is applied after a first predetermined delay time transpires from when the write command is received at the first set of pins; and

a second set of pins coupled to the third interconnect, the second set of pins to receive the write data after a predetermined write delay time has transpired from when the write command is received at the first set of pins, the second set of pins to provide the read data to the third interconnect after a predetermined read delay time transpires from when the read command is received at the first set of pins, wherein the predetermined write delay time is based on the predetermined read delay time.

11. The system of claim 10, wherein the predetermined write delay time is a channel turnaround time less than the predetermined read delay time.

12. The system of claim 10, wherein:

the second interconnect conveys an activate command;

the first set of pins receives the activate command; and

wherein the memory core comprises memory cells, and the integrated circuit memory device further comprises a third set of pins to receive a row address, a first column address and a second column address, wherein;

the activate command specifies that the memory device sense a row of the memory cells identified by the row address;

the first column address identifies a column location at which to store the write data; and

the second column address identifies a column location at which to obtain the read data.

13. The system of claim 12, wherein

the first set of pins receives, from the second interconnect, the activate command during a first command cycle, the write command during a second command cycle and the read command during a third command cycle;

and

the third set of pins receives the row address during the first command cycle, the first column address during the second command cycle, and the third column address during the third command cycle.

14. The system of claim 10, wherein the first set of pins receives, from the second interconnect, an activate command, a row address, a first column address and a second column address, wherein the activate command specifies that the memory device sense a row of memory cells in the memory core, the first column address identifies a column location at which to store the write data;

and the second column address identifies a column location at which to obtain the read data, wherein;

the activate command and the row address are included in a first packet;

the write command and the first column address are included in a second packet; and

the read command and the third column address are included in a third packet.

15. The system of claim 14, wherein:

the first packet is conveyed over a first portion of the second interconnect;

the second packet is conveyed over a second portion of the second interconnect; and

the third packet is conveyed over the second portion of the second interconnect.

16. A system comprising:

a first interconnect to convey a clock signal;

a second interconnect to convey;

a write command that specifies storage of write data in a memory core during a write operation; and

a read command that specifies output of read data accessed from the memory core;

a third interconnect to convey the write data and the read data;

an integrated circuit memory device comprising;

a pin coupled to the first interconnect, the pin to receive the clock signal from the first interconnect;

a first set of pins coupled to the second interconnect, the first set of pins to receive the write command from the second interconnect, wherein, in response to the write command, the write operation is initiated in the integrated circuit memory device after a predetermined delay time transpires; and

a second set of pins coupled to the third interconnect, the second set of pins to receive the write data, each pin of the second set of pins that receives write data to receive a first bit of the write data on a rising edge of the clock signal and a second bit of the write data on a falling edge of the clock signal, the second set of pins to provide the read data to the third interconnect, each pin of the second set of pins to provide a first bit of the read data on a rising edge of the clock signal and a second bit of the read data on a falling edge of the clock signal.

17. The system of claim 16, wherein:

the second set of pins receives the write data after a write delay time has transpired from when the write command is received at the first set of pins; and

wherein the second set of pins provides the read data after a read delay time transpires from when the read command is received at the first set of pins, wherein the write delay time is based on the read delay time, such that the write delay time is a channel turnaround time less than the read delay time.

18. A system comprising:

a first set of interconnect resources to convey;

a sense command;

after conveying the sense command, a write command that specifies a write operation; and

after conveying the write command, a read command that specifies a read operation;

a second set of interconnect resources to convey a row address that identifies a row of a memory array to sense in response to the sense command;

a third set of interconnect resources to convey data bits; and

a memory device comprising;

a memory core including a plurality of memory cells;

a first set of pins coupled to the first set of interconnect resources, the first set of pins to receive the sense command, the write command, and the read command, wherein, in response to the write command and after a first delay time transpires from when the write command is received, the memory device asserts a control signal to convey a plurality of data bits to the row identified by the row address;

a second set of pins coupled to the second set of interconnect resources, the second set of pins to receive the row address; and

a third set of pins coupled to the third set of interconnect resources, the third set of pins to receive the plurality of data bits after a second delay time has transpired from when the write command is received at the first set of pins, the third set of pins to output read data in response to the read command, wherein the read data is output after a third delay time has transpired from when the read command is received at the first set of pins, wherein the second delay time is based on the third delay time.

19. The system of claim 18, wherein the second delay time is based on the third delay time such that the second delay time is a channel turnaround time less than the third delay time.

20. The system of claim 18, wherein the memory device further comprises a plurality of sense amplifiers to sense, in response to the sense command, data stored in the row identified by the row address, and wherein the plurality of memory cells are dynamic memory cells.

21. A method of operation in a system that includes a memory device having a memory core, the method comprising:

conveying, to the memory device and over a first interconnect, a sense command that specifies that the memory device activate a row of memory cells in the memory core;

conveying, to the memory device and over a second interconnect, a row address that identifies the row;

conveying, to the memory device and over the first interconnect, a write command that specifies that the memory device receive write data, wherein, in response to the write command and after a first delay time transpires from when the write command is received by the memory device, the memory device asserts a control signal to store the write data in the row;

conveying, to the memory device and over the first interconnect, a read command that specifies that the memory device output read data, wherein in response to the read command and after a second delay time transpires from when the read command is received by the memory device, the memory device outputs the read data; and

conveying write data to the memory device, wherein the write data is conveyed after a third delay time has transpired from when the write command was conveyed to the memory device, wherein the third delay time is based on the second delay time.

22. The method of claim 21, further including:

conveying, to the memory device and over the second interconnect, a first column address that identifies a location in the row in which to store the write data; and

conveying, to the memory device and over the second interconnect, a second column address that identifies a location in the row in which to obtain the read data.

23. The method of claim 21, wherein the third delay time is based on the second delay time such that the third delay time is a channel turnaround time less than the second delay time.

24. The method of claim 21, wherein the sense command and the row address are conveyed to the memory device together during a clock cycle of a clock signal used in the system.

25. A method of operation in a system that includes a memory device having a memory core that includes a plurality of memory cells, the method comprising:

conveying, to the memory device, a sense command that specifies that the memory device activate a row of memory cells of the plurality of memory cells;

conveying, to the memory device, a row address that identifies the row;

conveying, to the memory device, a bank address that identifies a bank of the memory core that contains the row;

conveying, to the memory device, a write command that specifies that the memory device receive write data, wherein, in response to the write command, the memory device initiates a write operation after a first delay time transpires from receiving the write command;

conveying, to the memory device, a column address that identifies a column location of an activated row of the memory core in which to store the write data;

conveying, to the memory device, a bank address that identifies a bank of the memory core that contains the column location; and

conveying the write data to the memory device after a second delay time has transpired from when the write command was conveyed to the memory device.

26. The method of claim 25, wherein the sense command is included in a first control packet and the write command is included in a second control packet.

27. The method of claim 26, wherein the row address and the bank address that identifies the bank of the memory core that contains the row are included in the first packet, and wherein the column address and the bank address that identifies the bank of the memory core that contains the column location are included in the second packet.

28. The method of claim 25, further comprising:

conveying, to the memory device, a read command that specifies that the memory device output data; and

receiving data from the memory device after a third delay time transpires from when the read command was conveyed to the memory device, wherein the second delay time is based on the third delay such that the second delay time is a channel turnaround time less than the third delay time.