Power fault handling method, apparatus, and system

• US 7,334,158 B2
• Filed: 06/29/2004
• Issued: 02/19/2008
• Est. Priority Date: 06/29/2004
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Fullerton, Mark N., Bibikar, Vasudev J.
• Primary Examiner(s): Baderman; Scott
• Assistant Examiner(s): Scarbery; Kevin D
• Application Number:
  US10/879,515
• Publication Number:
  US 20050289393A1
• Time in Patent Office: 1,330 Days
• Field of Search: 714/14, 714/22, 714/36, 713/330, 713/340, 713320-324
• US Class Current: 714/14
• CPC Class Codes: G06F 1/30 Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations for resetting only G06F1/24
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 11/0721 within a central processing unit [CPU]
• CPC Class Codes: G06F 11/0772 Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers

Abstract

A processor may receive multiple signals corresponding to potential power faults. A control register in the processor may specify actions to be taken for each of the potential power faults.

Claims

1. A method comprising:

receiving one of a plurality of power fault indications;

accessing a control register programmed to separately specify for each of the plurality of power fault indications whether software intervention is to be allowed, wherein the control register includes more than one control bit for each of the plurality of power fault indications; and

conditionally allowing software intervention and entering a reduced power state based on contents of the control register and the identity of the power fault indication.

2. The method of claim 1 wherein conditionally allowing software intervention and entering a reduced power state comprises entering a reduced power state without allowing software intervention.

3. The method of claim 1 wherein conditionally allowing software intervention and entering a reduced power state comprises alerting a processor core of the power fault indication and allowing software intervention.

4. The method of claim 1 wherein receiving one of a plurality of power fault indications comprises receiving a main power supply fault indication or a backup power supply fault indication.

5. A method comprising:

waking up from a reduced power state;

examining a register that specifies which of a plurality of power faults caused the reduced power state and whether for each of the plurality of power faults software intervention was allowed when entering the reduced power state;

if the reduced power state was entered as a result of a power fault that allowed software intervention, retrieving saved state information and entering a non-reduced power state; and

if the reduced power state was entered as a result of a power fault that did not allow software intervention, entering the non-reduced power state without retrieving saved state information.

6. The method of claim 5 wherein examining a register comprises examining a register that includes a plurality of status bits, wherein each of the plurality of status bits corresponds to one of the plurality of power faults.

7. An article comprising:

a machine-readable medium having instructions stored thereon that when accessed result in a machine performing;

waking up from a reduced power state;

examining a register that specifies which of a plurality of power faults caused the reduced power state and whether for each of the plurality of power faults software intervention was allowed when entering the reduced power state;

if the reduced power state was entered as a result of a power fault that allowed software intervention, retrieving saved state information and entering a non-reduced power state; and

if the reduced power state was entered as a result of a power fault that did not allow software intervention, entering the non-reduced power state without retrieving saved state information.

8. The article of claim 7 wherein examining a register comprises examining a register that includes a plurality of status bits, wherein each of the plurality of status bits corresponds to one of the plurality of power faults.

9. A processor comprising:

a register to hold a separate control bit for each of a plurality of potential power faults, wherein each of the separate control bits specify whether software intervention is to be allowed when a corresponding power fault occurs; and

a state machine coupled to the register to receive power fault signals corresponding to the plurality of potential power faults, and to perform an operation when a power fault is received, wherein the operation includes allowing software intervention when specified by the control bit for the received power fault, and the operation further includes causing the processor to enter a reduced power state without allowing software intervention when specified by the control bit for the received power fault;

wherein the register includes multiple control bits for each of the plurality of potential power faults.

10. A processor comprising:

a register to hold a separate control bit for each of a plurality of potential power faults, wherein each of the separate control bits specify whether software intervention is to be allowed when a corresponding power fault occurs; and

a state machine coupled to the register to receive power fault signals corresponding to the plurality of potential power faults, and to perform an operation when a power fault is received, wherein the operation includes allowing software intervention when specified by the control bit for the received power fault, and the operation further includes causing the processor to enter a reduced power state without allowing software intervention when specified by the control bit for the received power fault;

wherein the register includes one control bit for each of two potential power faults.

11. The processor of claim 10 wherein the register further includes one status bit for each of the two potential power faults.