Intra-clip power and test signal generation for use with test structures on wafers

• US 7,339,388 B2
• Filed: 08/25/2004
• Issued: 03/04/2008
• Est. Priority Date: 08/25/2003
• Status: Active Grant

• Current Assignee: Tau-Metrix, Inc.
• Original Assignee: Tau-Metrix, Inc.
• Inventors: Pakdaman, Nader, Aghababazadeh, Majid, Steinbrueck, Gary L., Vickers, James S., Estabil, Jose J.
• Primary Examiner(s): KARLSEN, ERNEST F
• Application Number:
  US10/927,406
• Publication Number:
  US 20050090916A1
• Time in Patent Office: 1,287 Days
• Field of Search: None
• US Class Current: 324/750.3
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/3025 Wireless interface with the DUT
• CPC Class Codes: G01R 31/31707 Test strategies methods for generation of test sequences G01R31/318371
• CPC Class Codes: G01R 31/31718 Logistic aspects, e.g. binning, selection, sorting of devices under test, tester/handler interaction networks, Test management software, e.g. software for test statistics or test evaluation, yield analysis mechanical aspects G01R31/2808, G01R31/2851
• CPC Class Codes: G01R 31/318505 Test of Modular systems, e.g. Wafers, MCM's
• CPC Class Codes: G01R 31/318511 Wafer Test
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.

Claims

1. A system of electrical components for evaluating a partially-fabricated wafer, wherein the system comprises:

a circuit element provided within an active region of a die of the wafer, wherein the circuit element is configured to be operational at a time period in which only some of a plurality of fabrication process steps have been performed for completing fabrication of the wafer, so that the circuit element is operational before a remainder of the die becomes operational;

one or more receivers provided in the active region of the die and connected to the circuit element, wherein the one or more receivers are configured to receive one or more inputs and to generate, during the time period and from the one or more inputs, one or more signals for use with the circuit element;

wherein before fabrication process steps are performed to enable the die to be operational, the circuit element is configured to be responsive to the one or more inputs by exhibiting an electrical activity, the electrical activity having a characteristic that is invariant during the time period and detectable by a probe without effecting a usability of a chip that is formed from the die; and

wherein at any given instance in the time period in which only some of a plurality of fabrication process steps have been performed for making the remainder of the die operational, the characteristic of the electrical activity exhibited by the circuit element is indicative of at least one of (i) a design of at least a portion of the active region of the die during the fabrication;

or (ii) one or more fabrication process steps.

2. The system of claim 1, wherein the one or more receivers are configured to generate a test signal or a trigger signal for the circuit element in response to receiving a power input that also energizes the circuit element.

3. The system of claim 1, wherein the one or more receivers are configured to receive a modulating input to generate one or more of a power signal, a test signal or a trigger signal.

4. The system of claim 1, wherein the one or more receivers include a power receiver that is configured to generate, as a response to the power input, a power signal for the circuit element.

5. The system of claim 4, wherein the power receiver is configured to receive the power input without contacting a source of the power input.

6. The system of claim 5, wherein the power receiver is configured to receive the power input as a radio-frequency transmission transmitted from the source.

7. The system of claim 5, wherein the power receiver is configured to receive the power input through an inductive or capacitive coupling with the source.

8. The system of claim 5, wherein the power receiver is configured to receive energy from an electron beam source.

9. The system of claim 5, wherein the power receiver is configured to receive energy front an ion beam source.

10. The system of claim 4, wherein the power receiver includes a voltage step-up to increase a voltage of the power signal before it is supplied to the circuit element.

11. The system of claim 4, wherein the power receiver includes a optical photoreceiver.

12. The system of claim 4, wherein:

the power receiver is configured to generate a power signal for the circuit element in response to receiving a constant energy beam;

and wherein the one or more receivers generate at least one of a test signal or a trigger signal for the circuit element in response to receiving a modulating energy beam.

13. The system of claim 1, wherein the circuit element is configured to exhibit the electrical activity corresponding to a detectable production of photons.

14. The system of claim 1, wherein the circuit element is configured to exhibit the electrical activity that results in an output signal from the circuit element.

15. The system of claim 1, further comprising:

a computing component that correlates the detected electrical activity to one or more performance parameters, and wherein the performance parameter of the circuit clement is individually or in combination with performance parameters of other circuit elements is indicative of the design or the one or more fabrication process steps.

16. The system of claim 1, wherein the electrical activity includes a photon emission that is detectable by a photoreceiver.

17. The system of claim 1, wherein the electrical activity includes an optoelectronic effect that is detectable by an optoelectronic probe.

18. The system of claim 1, wherein the electrical activity includes a varying voltage that is detectable through a capacitive coupling.

19. The system of claim 1, wherein the electrical activity includes a varying current that is detectable through an inductive coupling.

20. The system of claim 1, wherein the electrical activity is a radio-frequency signal output that is detectable by a radio-frequency receiver.

21. The system of claim 1, wherein the electrical activity is a varying voltage that is detectable by an electron beam.

22. The system of claim 1, wherein the characteristic is selected from a group consisting of (i) a slew rate, (ii) a phase shift delay, (iii) a frequency, (iv) a time delay, (v) a quantity, and (vi) a current or voltage amplitude.

23. The system of claim 2, wherein the energy input corresponds to one of a light input, electron beam, radio-frequency signal, a capacitive coupling, an inductive coupling, or an ion beam.

24. The system of claim 1, wherein the one or more receivers in the active region include a first receiver for receiving a power input and a second receiver for receiving a test or a trigger signal input.

25. The system of claim 1, wherein the one or more receivers are configured to generate an enabling signal for the circuit element in response to receiving the one or more inputs.

26. The system of claim 1, wherein the one or more receivers are configured to receive an input to generate one or more of a power signal, a test signal or a trigger signal without contacting a source of the input.