Reconfigurable memory module and method

• US 7,343,444 B2
• Filed: 09/15/2006
• Issued: 03/11/2008
• Est. Priority Date: 06/19/2003
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Jeddeloh, Joseph M., Lee, Terry R.
• Primary Examiner(s): Sough; Hyung
• Assistant Examiner(s): Walter; Craig E
• Application Number:
  US11/522,175
• Publication Number:
  US 20070011392A1
• Time in Patent Office: 543 Days
• Field of Search: None
• US Class Current: 711/5
• CPC Class Codes: G06F 12/0661 and decentralised selection
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/4239 with asynchronous protocol

Abstract

A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices divided into a plurality of ranks. The memory hub is operable to configure the memory module to simultaneously address any number of ranks to operate in a high bandwidth mode, a high memory depth mode, or any combination of such modes.

Claims

1. A memory system, comprising:

a controller operable to receive a memory request and to transmit a corresponding memory request to an input/output port;

a plurality of memory modules, each of the memory modules comprising;

a plurality of memory devices arranged in a plurality of ranks; and

a memory hub operable to receive a memory request at an input/output port, the memory hub being coupled to the memory devices in each of the ranks, the memory hub being programmable to configure the memory module containing the memory hub in one of a plurality of modes;

wherein the memory hub in a first of the memory modules is programmed such that the programming configures the first memory module so that all of the ranks of memory devices in the first memory module simultaneously respond to being addressed, the memory hub in a second of the memory modules is programmed such that the programming configures the second memory module so that half and only half of the ranks of memory devices in the second memory module simultaneously respond to being addressed, and the memory hub in a third of the memory modules is programmed such that the programming configures the third memory module so that each of the ranks of memory devices in the third memory module individually respond to being addressed; and

a communications link coupling the input/output port of the controller to the input/output ports of the memory hubs in the respective memory modules.

2. The memory system of claim 1 wherein the memory hub in each of the memory modules is coupled to the memory devices in each of the ranks through respective busses.

3. The memory system of claim 1, further comprising a programmable storage device coupled to the memory hub, the programmable storage device being programmed to control the operating mode of the memory hub.

4. The memory system of claim 1 wherein the memory devices in each rank are collectively operable to read or write N-bit data words, and wherein the memory hub further comprises an input/output port that is operable to receive or transmit M*N-bit data words, where M is the number of ranks of memory devices in the memory module.

5. The memory system of claim 1 wherein the memory devices in each rank are collectively operable to read or write N-bit data words in a first period of time, and wherein the memory hub further comprises an input/output port that is operable to receive or transmit M*N data bits in the first period of time, where M is the number of ranks of memory devices in the memory module.

6. The memory system of claim 5 wherein the memory devices are operable to read or write data at a rate of X bits per second, and wherein the input/output port comprises an N-bit input/output port that is operable to transmit or receive N-bit data words at a rate of M*X data words per second.

7. The memory system of claim 5 wherein the memory devices are operable to read or write data at a rate of X bits per second, and wherein the input/output port comprises a 2*N-bit input/output port that is operable to transmit or receive 2*N-bit data words at a rate of M*X/2 data words per second.

8. The memory system of claim 5 wherein the memory devices are operable to read or write data at a rate of X bits per second, and wherein the input/output port comprises a M*N-bit input/output port that is operable to transmit or receive M*N-bit data words at a rate of X data words per second.

9. The memory system of claim 1 wherein the memory devices comprise dynamic random access memory devices.

10. The memory system of claim 9 wherein the dynamic random access memory devices comprise synchronous dynamic random access memory devices.

11. The memory system of claim 1 wherein the input/output port of the controller and the input/output port of each of the memory hubs comprises an optical input/output port, and wherein the communications link comprises an optical communications link.

12. A computer system, comprising:

a central processing unit (“

CPU”

);

a system controller coupled to the CPU, the system controller being operable to receive a memory request from the central processing unit and to transmit a corresponding memory request to an input/output port;

an input device coupled to the CPU through the system controller;

an output device coupled to the CPU through the system controller;

a storage device coupled to the CPU through the system controller;

a plurality of memory modules, each of the memory modules comprising;

a plurality of memory devices arranged in a plurality of ranks; and

a memory hub operable to receive a memory request at an input/output port, the memory hub being coupled to the memory devices in each of the ranks, the memory hub being programmable to configure the memory module containing the memory hub in one of a plurality of modes;

wherein the memory hub in a first of the memory modules is programmed such that the programming configures the first memory module so that all of the ranks of memory devices in the first memory module simultaneously respond to being addressed, the memory hub in a second of the memory modules is programmed such that the programming configures the second memory module so that half and only half of the ranks of memory devices in the second memory module simultaneously respond to being addressed, and the memory hub in a third of the memory modules is programmed such that the programming configures the third memory module so that each of the ranks of memory devices in the third memory module individually respond to being addressed; and

a communications link coupling the input/output port of the system controller to the input/output ports of the memory hubs in the respective memory modules.

13. The computer system of claim 12 wherein the memory hub in each of the memory modules is coupled to the memory devices in each of the ranks through respective busses.

14. The computer system of claim 12 further comprising a programmable storage device coupled to the memory hub, the programmable storage device being programmed to control the operating mode of the memory hub.

15. The computer system of claim 12 wherein the memory devices in each rank are collectively operable to read or write N-bit data words, and wherein the memory hub further comprises an input/output port that is operable to receive or transmit M*N-bit data words, where M is the number of ranks of memory devices in the memory module.

16. The computer system of claim 12 wherein the memory devices in each rank are collectively operable to read or write N-bit data words in a first period of time, and wherein the memory hub further comprises an input/output port that is operable to receive or transmit M*N data bits in the first period of time, where M is the number of ranks of memory devices in the memory module.

17. The computer system of claim 16 wherein the memory devices are operable to read or write data at a rate of X bits per second, and wherein the input/output port comprises an N-bit input/output port that is operable to transmit or receive N-bit data words at a rate of M*X data words per second.

18. The computer system of claim 16 wherein the memory devices are operable to read or write data at a rate of X bits per second, and wherein the input/output port comprises a 2*N-bit input/output port that is operable to transmit or receive 2*N-bit data words at a rate of M*X/2 data words per second.

19. The computer system of claim 16 wherein the memory devices are operable to read or write data at a rate of X bits per second, and wherein the input/output port comprises a M*N-bit input/output port that is operable to transmit or receive M*N-bit data words at a rate of X data words per second.

20. The computer system of claim 12 wherein the memory devices comprise dynamic random access memory devices.

21. The computer system of claim 20 wherein the dynamic random access memory devices comprise synchronous dynamic random access memory devices.