Bias circuit for BJT amplifier

• US 7,345,547 B2
• Filed: 10/17/2005
• Issued: 03/18/2008
• Est. Priority Date: 10/17/2005
• Status: Active Grant

• Current Assignee: WJ Communications, Inc. (Qorvo, Inc.)
• Original Assignee: WJ Communications, Inc. (Qorvo, Inc.)
• Inventors: Wang, Nanlei Larry, Strifler, Walter A.
• Primary Examiner(s): NGUYEN, KHANH V
• Application Number:
  US11/253,203
• Publication Number:
  US 20070096823A1
• Time in Patent Office: 883 Days
• Field of Search: 330/285, 330/296
• US Class Current: 330/285
• CPC Class Codes: H03F 1/30 Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in differential amplifiers H03F3/45479
• CPC Class Codes: H03F 1/32 Modifications of amplifiers to reduce non-linear distortion by negative feedback H03F1/34
• CPC Class Codes: H03F 2200/18 the bias of the gate of a FET being controlled by a control signal
• CPC Class Codes: H03F 2200/222 A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier
• CPC Class Codes: H03F 2200/391 the output circuit of an amplifying stage comprising an LC-network
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 3/191 Tuned amplifiers H03F3/193, H03F3/195 take precedence
• CPC Class Codes: H03F 3/605 Distributed amplifiers

Abstract

The embodiments of the present invention include a bias circuit for a power-amplifying device, which receives and amplifies an input RF signal having a series of RF cycles within a modulation envelop. The bias circuit compensates odd-order distortion processes by detecting the power in the input signal and providing a dynamic adjustment to a bias stimulus for the power-amplifying device within a time scale of the modulation envelope.

Claims

1. A radio frequency (RF) amplifier circuit having an input terminal for receiving a RF input signal, comprising:

a RF power-amplifying transistor having a base coupled to the input terminal;

a bias circuit coupled to the input terminal and to the RF power-amplifying transistor, the bias circuit including a bypass capacitor and a PN junction diode having first and second terminals, the first terminal being coupled to the base of the RF amplifying transistor through at least one impedance element, the second terminal is coupled to a RF ground in the RF amplifier circuit through the bypass capacitor

wherein the bias circuit is configured to raise a voltage at the base of the RF power-amplifying transistor in response to an increase in an RF power level in the RF input signal; and

the PN junction diode is part of a detecting transistor having a base and a collector, the RF amplifier circuit further comprising;

a reference voltage terminal for connecting to a reference voltage supply;

a bias voltage terminal for connecting to a bias voltage supply;

a first bias transistor having a collector coupled to the reference voltage supply through a reference resistor, an emitter coupled to a circuit ground terminal through a first emitter degeneration resistor, and a base; and

a second bias transistor coupled with the detecting transistor in a current mirror configuration, the second bias transistor having a base connected to the base of the detecting transistor at a common connected base node, an emitter coupled to the base of the first bias transistor through a second emitter degeneration resistor, and a collector coupled to the bias voltage terminal.

2. The RF amplifier circuit of claim 1, wherein each of the at least one impedance element includes a two-port impedance network.

3. The RF amplifier circuit of claim 1, wherein the PN junction diode is part of a detecting transistor having a base and a collector that are tied to each other.

4. The RF amplifier circuit of claim 1, wherein the bypass capacitor is coupled between the common connected base node and the circuit ground.

5. The RF amplifier circuit of claim 1, further comprising a buffer transistor having a base coupled to the reference voltage terminal through the reference resistor, an emitter coupled to the common connected base node, and a collector coupled to the bias voltage terminal.

6. The RF amplifier circuit of claim 1, wherein the PN junction diode is part of a detecting transistor having a base and a collector, the RF amplifier circuit further comprising:

a reference voltage terminal for connecting to a reference voltage supply;

a first bias transistor having an emitter coupled to a circuit ground terminal through a first emitter degeneration resistor, and a base and a collector tied with each other; and

a second bias transistor coupled with the detecting transistor in a current mirror configuration, the second bias transistor having a base connected to the base of the detecting transistor at a common connected base node, an emitter coupled to the tied base and connector of the first bias transistor through a second emitter degeneration resistor, and a collector tied to the base of the second bias transistor and coupled to the reference voltage terminal via a reference resistor.

7. The RF amplifier circuit of claim 6, further comprising

a bias voltage terminal for connecting to a bias voltage supply, wherein the detecting transistor has a collector coupled to the bias voltage terminal;

and

a negative feedback network coupled between the collector of the detecting transistor and the common connected base node, the negative feedback network including a resistor and a capacitor serially connected with each other.

8. The RF amplifier circuit of claim 1, further comprising:

a reference voltage terminal for connecting to a reference voltage supply;

a tier of serially connected level-shifting diodes coupled between the reference voltage terminal and a circuit ground;

a bias transistor having an emitter coupled to the PN junction diode, a base coupled to the tier of serially connected level-shifting diodes, and a collector coupled to the base of the bias transistor through a negative feedback network.

9. The RF amplifier circuit of claim 8, wherein the tier of serially connected level-shifting diodes includes first, second and third bias transistors and first, second, and third emitter degeneration resistors, each of the first, second and third bias transistors having a base and a collector tied with each other and an emitter coupled to respective ones of the first, second, and third emitter degeneration resistors.