Apparatus and methods for adjusting performance of programmable logic devices

• US 7,348,827 B2
• Filed: 05/19/2004
• Issued: 03/25/2008
• Est. Priority Date: 05/19/2004
• Status: Expired due to Fees

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Rahim, Irfan, Pedersen, Bruce, Liu, Yow-Juang W., McElheny, Peter
• Primary Examiner(s): Tan; Vibol
• Application Number:
  US10/848,953
• Publication Number:
  US 20050258862A1
• Time in Patent Office: 1,406 Days
• Field of Search: 327/534, 327/537, 257/500, 326/38, 326/39, 326/41
• US Class Current: 327/534
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: H03K 19/00369 Modifications for compensating variations of temperature, supply voltage or other physical parameters
• CPC Class Codes: H03K 19/1731 Optimisation thereof
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET

Abstract

A programmable logic device (PLD) includes mechanisms for adjusting or setting the body bias of one or more transistors. The PLD includes a body-bias generator. The body-bias generator is configured to set a body bias of one or more transistors within the programmable logic device. More specifically, the body-bias generator sets the body bias of the transistor(s) so as to trade off performance and power consumption of the transistor(s).

Claims

1. A programmable logic device (PLD), comprising:

a control circuitry;

a body-bias generator coupled to the control circuitry, the body-bias generator configured to set a body bias of a transistor within the programmable logic device (PLD); and

a variable impedance device coupled to the control circuitry, the variable impedance device configured to control power dissipation of a first circuit within the programmable logic device (PLD), wherein the first circuit comprises a circuit unused in an electronic circuit implemented by the programmable logic device (PLD).

2. The programmable logic device (PLD) according to claim 1, wherein the variable impedance device comprises a field-effect transistor (FET).

3. The programmable logic device (PLD) according to claim 2, wherein the body-bias generator is configured to set the body bias of the transistor so as to avoid thermal runaway within the programmable logic device (PLD).

4. The programmable logic device (PLD) according to claim 2, wherein the body-bias generator is further configured to adjust the body bias of the transistor so as to trade off performance and power consumption of the transistor.

5. The programmable logic device (PLD) according to claim 4, wherein the body-bias generator is further configured to adjust the body bias of the transistor so as to optimize the tradeoff between the performance and power consumption of the transistor.

6. The programmable logic device (PLD) according to claim 1, wherein the variable impedance device is further configured to shut down the first circuit by interrupting a supply of power to the first circuit.

7. The programmable logic device (PLD) according to claim 6, wherein the supply of power to the first circuit is provided by a supply-voltage circuit within the programmable logic device (PLD).

8. A programmable logic device (PLD), comprising:

a temperature sensor, the temperature sensor configured to sense a temperature of a first circuit in the programmable logic device (PLD);

a body-bias generator configured to set a body bias of a set of transistors in response to a control signal; and

a control circuit coupled to the temperature sensor and the body-bias generator, the control circuit configured to provide the control signal in response to a signal received from the temperature sensor.

9. The programmable logic device (PLD) according to claim 8, wherein the control circuit is further configured to provide the control signal so as to avoid thermal runaway in the set of transistors.

10. The programmable logic device (PLD) according to claim 8, wherein the control circuit is further configured to provide the control signal so as to trade off performance and power consumption of the set of transistors.

11. The programmable logic device (PLD) according to claim 10, wherein the control circuit is further configured to provide the control signal so as to optimize the tradeoff between the performance and power consumption of the set of transistors.

12. The programmable logic device (PLD) according to claim 8, wherein the set of transistors resides in the first circuit.

13. The programmable logic device (PLD) according to claim 8, wherein the control circuit is further configured to derive the control signal from a reference signal and a signal received from the temDerature sensor.

14. A programmable logic device (PLD), comprising:

means for deriving a body-bias signal from at least one parameter related to the programmable logic device (PLD); and

means for providing the body-bias signal to a transistor in a first circuit within the programmable logic device (PLD) in response to an input signal provided by a configuration memory (CRAM), wherein the at least one parameter comprises either a temperature level or control information provided by a source external to the programmable logic device (PLD).

15. A programmable logic device (PLD), comprising:

means for deriving a body-bias signal from at least one parameter related to the programmable logic device (PLD); and

means for providing the body-bias signal to a transistor in a first circuit within the programmable logic device (PLD) in response to an input signal, wherein the at least one parameter comprises either a temperature level or control information provided by a source external to the programmable logic device (PLD), wherein the first circuit comprises a controller.