Configurable inputs and outputs for memory stacking system and method

• US 7,352,602 B2
• Filed: 12/30/2005
• Issued: 04/01/2008
• Est. Priority Date: 12/30/2005
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Janzen, Jeffery W.
• Primary Examiner(s): Nguyen; Viet Q.
• Application Number:
  US11/323,530
• Publication Number:
  US 20070153588A1
• Time in Patent Office: 823 Days
• Field of Search: 365/63, 326/47, 326/41, 257/686, 257/698, 438/109, 174/524, 361/790
• US Class Current: 365/63
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/109 Control signal input circuits
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/225 Clock input buffers
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/01055 Cesium [Cs]

Abstract

Embodiments of the present invention relate to configurable inputs and/or outputs for memory and memory stacking applications. More specifically, embodiments of the present invention include memory devices that include a die having a circuit configured for enablement by a particular signal, an input pin configured to receive the particular signal, and a path selector configured to selectively designate a signal path to the circuit from the input pin.

Claims

1. A memory device comprising:

a first die comprising;

a first circuit configured to be enabled by a first control signal;

a first input pin configured to receive the first control signal; and

a first path selector arranged between the first input pin and the first circuit and configured to select a first signal path to the first circuit from the first input pin; and

a second die comprising;

a second circuit configured to be enabled by a second control signal;

a second input pin configured to receive the second control signal; and

a second path selector arranged between the second input pin and the second circuit and configured to select a second signal path to the second circuit from the second input pin, wherein the first die and the second die form a stack such that a signal may be routed though each of the first signal path and the second signal path in a direction perpendicular to a surface of the first die and a surface of the second die, wherein the surface of the second die is disposed parallel to the surface of the first die.

2. The memory device of claim 1, wherein the first control signal is a chip select signal.

3. The memory device of claim 1, wherein the first path selector comprises a multiplexer.

4. The memory device of claim 1, comprising a path selector control circuit comprising a fuse, wherein the path selector control circuit is configured to control the first path selector.

5. The memory device of claim 4, wherein the path selector control circuit is configured to provide a high signal when the fuse is blown.

6. The memory device of claim 4, wherein the path selector control circuit is configured to provide a low signal when an antifuse is blown.

7. The memory device of claim 1, comprising memory comprising a plurality of die.

8. A memory module comprising:

a die stack comprising a plurality of memory devices;

a plurality of pins disposed within the plurality of memory devices, wherein each of the plurality of pins is configured to receive a signal;

a plurality of circuits disposed within each of the plurality of memory devices; and

a plurality of path selectors configured to selectively provide signal paths between the plurality of pins and the plurality of circuits, wherein a plurality of signals may be routed through the signal paths such that each of the plurality of signals enters the die stack from pins selected from the plurality of pins, the pins being disposed on a bottom surface of the die stack and each of the plurality of signals routing upward through the signal paths in a direction perpendicular to the bottom surface.

9. The memory module of claim 8, wherein the memory module comprises a dual inline memory module (DIMM).

10. The memory module of claim 8, wherein each of the plurality of memory devices comprises a dynamic random access memory (DRAM) device.

11. The memory module of claim 8, wherein the plurality of signals include a chip select signal, a clock enable signal, an on-die termination signal, and a calibration signal.

12. The memory module of claim 8, wherein the plurality of path selectors comprises at least one multiplexer.

13. The memory module of claim 8, wherein the plurality of path selectors comprises at least one path selector control circuit comprising a fuse or antifuse, wherein the path selector control circuit is configured to control the path selector.

14. The memory module of claim 13, wherein the path selector control circuit is configured to provide a high signal when the fuse is blown.

15. The memory module of claim 13, wherein the path selector control circuit is configured to provide a low signal when the antifuse is blown.

24. The memory module of claim 8, wherein each of the plurality of circuits is configured to be enabled by control signals, the control signals communicatively coupling the path selectors between the plurality of pins and the plurality of circuits.

25. The memory module of claim 8, wherein the memory devices include four ×

8 devices configurable as two ranks of ×

16 memory stacked on a single side of the memory module.

16. A computer system comprising:

a processor; and

a memory system coupled to the processor and comprising;

a memory controller;

a memory device comprising a die stack;

a first circuit in a first die of the die stack and a second circuit in a second die of the die stack, wherein the first and second circuits are configured to be enabled by a control signal;

a first input pin disposed within the first die on a bottom surface of the die stack, the first input pin configured to receive the control signal;

a first path selector arranged between the first input pin and the first circuit and configured to select a first signal path to the first circuit from the first input pin based on the control signal; and

a second input pin disposed within the second die in a position in-line with and above the first input pin, the second input pin configured to receive the control signal;

a second path selector arranged between the second input pin and the second circuit and configured to select a second signal path to the second circuit from the second input pin based on the control signal such that a signal may be routed though each of the first signal path and the second signal path in a direction perpendicular to the bottom surface of the die stack.

17. The memory system of claim 16, wherein the memory device comprises a dynamic random access memory (DRAM) device.

18. The memory system of claim 16, wherein the control signal comprises a chip select signal.

19. The memory system of claim 16, wherein the control signal comprises an inverse chip select signal.

20. The memory system of claim 16, wherein the first path selector comprises a fuse controlled path selector.

21. The memory system of claim 20, wherein the fuse controlled path selector includes an antifuse.

22. A method of manufacturing memory, comprising:

providing a plurality of memory die having a fuse controlled path selector within each of the memory die;

enabling communication paths to circuits within each memory die based on enablement requirements of the circuits; and

configuring the plurality of memory die in a stack to route a signal from an input pin disposed on a bottom surface of the stack though the die stack in a direction perpendicular to the bottom surface of the stack via the enabled communication paths.

23. The method of claim 22, comprising configuring the plurality of memory die in the stack without providing a redistribution layer.