Reduced power usage in a memory for a programmable logic device

• US 7,352,647 B1
• Filed: 12/22/2005
• Issued: 04/01/2008
• Est. Priority Date: 12/22/2005
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Saini, Rahul
• Primary Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US11/317,324
• Time in Patent Office: 831 Days
• Field of Search: 365/205, 365/230.03, 365/230.06, 365/230.08, 326 37- 40
• US Class Current: 365/230.03
• CPC Class Codes: G11C 11/413 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out

Abstract

A method and system to reduce power usage of memory within a programmable logic device (PLD) is disclosed. In one embodiment, a memory block is formed from a plurality of memory sub-blocks. A data management circuit is used to programmably couple bitlines and/or wordlines to a selected number of memory sub-blocks necessary for respective read/write operations. During a respective read operation, the data management circuit uses row and/or column addresses to determine which memory bitlines and/or wordlines, and memory sub-blocks are essential in the read operation, leaving other non-essential bitlines and/or wordlines, and memory sub-blocks idle, thereby conserving power usage of the entire memory block. In one embodiment, a during respective read operation, a series of programmable pass-gates are used to selectively de-couple bitlines and/or wordlines, and memory sub-blocks that are not essential to the read operation.

Claims

1. A programmable logic device comprising:

a memory block having a plurality of memory sub-blocks;

a data control circuit that selectively connects charged read/write lines to one or more of the memory sub-blocks, wherein during a read operation the data control circuit connects charged read/write lines to only those memory sub-blocks necessary for the read operation,

wherein the data control circuit comprises a select line, wherein the select line causes the data control circuit to connect respective data read/write lines of at least two memory sub-blocks together in response to a signal indicative of connecting the data read/write lines, and wherein the signal comprises a most significant bit.

2. The programmable logic device of claim 1, wherein during a write data operation the data control circuit connects together respective read/write lines associated with the plurality of memory sub-blocks.

3. The programmable logic device of claim 1, wherein the read/write lines comprise bitlines or wordlines.

4. The programmable logic device of claim 1, wherein the data control circuit is a switch capable of connecting a first set of read/write lines associated with a first memory sub-block to a second set of read/write lines associated with a second memory sub-block.

5. The programmable logic device of claim 1, wherein the data control circuit comprises a transistor switch.

6. The programmable logic device of claim 1, wherein data control circuit decouples at least one data read/write line not used for the read operation.

7. The programmable logic device of claim 1, further comprising at least one address decoder capable of being enabled when needed and disabled when not needed.

8. An integrated circuit comprising:

a memory block having a plurality of memory sub-blocks;

a data switching circuit that selectively connects charged read/write lines to the plurality of memory sub-blocks, wherein during a read operation the data switching circuit decouples at least some of the read/write lines and memory sub-blocks not needed to perform the read operation;

wherein during a write data operation that writes data received on data lines extending from an external device into the memory block, the data switching circuit connects together respective read/write lines associated with the plurality of memory sub-blocks.

9. The integrated circuit of claim 8, wherein the read/write lines comprise bitlines.

10. The integrated circuit of claim 8, wherein the read/write lines comprise wordlines.

11. The integrated circuit of claim 8, wherein the data switching circuit comprises transistors, wherein each transistor provides a switching connection between a respective first bitline and a respective second bitline.

12. The integrated circuit of claim 8, wherein the data switching circuit comprises transistors, wherein each transistor provides a switching connection between a respective first wordline and a respective second wordline.

13. The integrated circuit of claim 8, wherein the data switching circuit comprises at least one transistor pass-gate.

14. The integrated circuit of claim 8, wherein the data switching circuit comprises a select line responsive to a logic signal, wherein when the logic signal is indicative of coupling the read/write lines, the select line causes the data switching circuit to couple at least some respective read/write lines together.

15. A method of reducing power consumption in a memory circuit, the method comprising:

during a memory read operation, determining a first set of read/write lines associated with a first portion of the memory circuit used for the data read operation;

determining a second set of read/write lines associated with a second portion of the memory circuit not used for the data read operation; and

decoupling the second set of read/write lines from the first set of read/write lines during the data read operation, wherein decoupling the second set of read/write lines from the first set of read/write lines comprises providing a switch between at least a first wordline and a respective second wordline.

16. The method of claim 15, wherein determining the first set of read/write lines comprises determining which memory sub-block is required for the memory read operation.

17. The method of claim 15, wherein determining the second set of read/write lines comprises determining which memory sub-block is required for the memory read operation.

18. The method of claim 15, wherein decoupling the second set of read/write lines from the first set of read/write lines comprises providing a switch between at least a first bitline and a respective second bitline.

19. The method e of claim 15, wherein decoupling the second set of read/write lines from the first set of read/write lines comprises isolating at least some of the bitlines used for the memory read operation from bitlines not used for the memory read operation.

20. The method of claim 15, wherein decoupling the second set of read/write lines from the first set of read/write lines comprises isolating at least some of the wordlines used for the memory read operation from wordlines not used for the memory read operation.

21. The method of claim 15, wherein decoupling the second set of read/write lines from the first set of read/write lines comprises isolating at least some of the memory sub-blocks used for the memory read operation from memory sub-blocks not used for the memory read operation.

22. The method of claim 15, wherein only one switch is used between the first wordline and the second wordline.

23. The method of claim 15, wherein the data switching circuit consists of only one transistor pass-gate.

24. The method of claim 15, further comprising:

determining a third set of read/write lines associated with a third portion of the memory circuit used for the data read operation;

determining a fourth set of read/write lines associated with a fourth portion of the memory circuit not used for the data read operation; and

decoupling the fourth set of read/write lines from the third set of read/write lines during the data read operation, wherein decoupling the fourth set of read/write lines from the third set of read/write lines comprises providing a switch between at least a first bitline and a respective second bitline.