Device to receive, buffer, and transmit packets of data in a packet switching network

• US 7,352,763 B2
• Filed: 01/20/2004
• Issued: 04/01/2008
• Est. Priority Date: 06/26/2000
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Burton, Tom E., Gasbarro, Dominic J., Leitner, Brian M., Susnow, Dean S.
• Primary Examiner(s): QURESHI, AFSAR M
• Application Number:
  US10/761,394
• Publication Number:
  US 20040151176A1
• Time in Patent Office: 1,533 Days
• Field of Search: 370/360, 370/386, 370/389, 370/395.54, 370/395.7, 370/412, 370/429, 370/392, 370/395.51, 709/212, 709/250
• US Class Current: 370/412
• CPC Class Codes: H04L 49/103 using a shared central buffer; using a shared memory
• CPC Class Codes: H04L 49/35 Switches specially adapted for specific applications
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/9036 Common buffer combined with individual queues
• CPC Class Codes: H04L 49/9057 Arrangements for supporting packet reassembly or resequencing
• CPC Class Codes: H04L 49/9063 Intermediate storage in different physical parts of a node or terminal
• CPC Class Codes: H04L 49/9068 in the network interface card
• CPC Class Codes: H04L 49/9089 replacing packets in a storage arrangement, e.g. pushout
• CPC Class Codes: H04L 69/22 Parsing or analysis of headers

Abstract

A device to create, receive, and transmit packets of data in a packet switching network. This device employs a direct memory access packet controller which would interface between memory contained within a computer system and a packet switched network. This direct memory access packet controller would utilize one or more micro-engines that would dynamically allocate buffer space to process received packets of data. This direct memory access packet controller would further utilize a transmit cell FIFO circuit to allocate buffer space to packets being transmitted. In addition, a sequencer would act to control the workflow of packets being received and transmitted.

Claims

1. A device comprising:

micro-engines to receive a packet, determine if a task is available to process the packet, and to assign the task and a buffer to store the packet, said micro-engines comprising;

first circuitry to extract from a packet header comprising the packet a value representing a queue, and to signal a sequencer that a micro-engine task and cell buffer are to be assigned for the packet; and

second circuitry to extract an opcode for the packet header, determine a number of bytes in the packet header, to determine a number of bytes in the packet payload, and to determine a number of bytes available in the cell buffer.

2. The device of claim 1, wherein the first circuitry comprises:

third circuitry to receive the packet and transmit a request that the micro-engine task be assigned to process the packet.

3. The device of claim 2, wherein:

the sequencer is capable of receiving the request that the micro-engine task be assigned to process the packet identifying if the micro-engine task is available to process the packet, and assigning the micro-engine task and the cell buffer to the packet.

4. The device of claim 3, wherein the first circuitry also comprises:

a counter to count a number of packets received by the third circuitry and to transmit to the sequencer another value representing the number of packets received by the third circuitry; and

first-in-first-out (FIFO) circuitry to receive the value representing the queue and to transmit to the sequencer the value representing the queue.

5. The device of claim 1, wherein the second circuitry comprises:

third circuitry to determine based upon the opcode a length of the packet header.