Three-dimensional device fabrication method

• US 7,354,798 B2
• Filed: 12/20/2002
• Issued: 04/08/2008
• Est. Priority Date: 12/20/2002
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Pogge, H. Bernhard, Yu, Roy
• Primary Examiner(s): Graybill; David E
• Application Number:
  US10/538,905
• Publication Number:
  US 20060121690A1
• Time in Patent Office: 1,936 Days
• Field of Search: None
• US Class Current: 438/109
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/03002 for supporting the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0345 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/03849 Reflowing
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/06519 including bonding areas providing primarily thermal dissipation
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13116 : Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/13144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/16145 : the bodies being stacked
• CPC Class Codes: H01L 2224/16146 : the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16147 : the bump connector connecting to a bonding area disposed in a recess of the surface
• CPC Class Codes: H01L 2224/16225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/17519 : including bump connectors providing primarily thermal dissipation
• CPC Class Codes: H01L 2224/29111 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/2919 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32145 : the bodies being stacked
• CPC Class Codes: H01L 2224/32225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73104 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/81 : using a bump connector
• CPC Class Codes: H01L 2224/81005 : being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/81141 : Guiding structures both on and outside the body
• CPC Class Codes: H01L 2224/81191 : wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81192 : wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81203 : Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/81385 : Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/81815 : Reflow soldering
• CPC Class Codes: H01L 2224/83 : using a layer connector
• CPC Class Codes: H01L 2224/83191 : wherein the layer connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83203 : Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/8385 : using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 2224/92 : Specific sequence of method steps
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06593 : Mounting aids permanently on device; arrangements for alignment use of temporary supports H01L21/6835
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/0132 : Binary Alloys
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/0695 : Polyamide
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: Y10S 438/977 : Thinning or removal of substrate

Abstract

A method is described for fabricating a three-dimensional integrated device including a plurality of vertically stacked and interconnected wafers. Wafers (1, 2, 3) are bonded together using bonding layers (26, 36) of thermoplastic material such as polyimide; electrical connections are realized by vias (12, 22) in the wafers connected to studs (27, 37). The studs connect to openings (13, 23) having a lateral dimension larger than that of the vias at the front surfaces of the wafers. Furthermore, the vias in the respective wafers need not extend vertically from the front surface to the back surface of the wafers. A conducting body (102) provided in the wafer beneath the device region and extending laterally, may connect the via with the matallized opening (103) in the back surface. Accordingly, the conducting path through the wafer may be led underneath the devices thereof. Additional connections may be made between openings (113) and studs (127) to form vertical heat conduction pathways between the wafers.

Claims

1. A method for fabricating a three-dimensional integrated device including a plurality of vertically stacked and interconnected wafers, the method comprising the steps of:

providing a first wafer having a front surface and a back surface, the first wafer having devices formed in a region adjacent to the front surface thereof;

forming a via in the first wafer extending from the front surface, the via being characterized by a lateral dimension at the front surface;

removing material from the first wafer at the back surface thereof;

forming an opening in the back surface of the first wafer, thereby exposing the via, the opening having a lateral dimension grater than said lateral dimension of the via;

forming a layer of conducting material in said opening;

providing a second wafer having a front surface and a back surface, the second wafer having devices formed therein adjacent to the front surface thereof;

forming a stud on the front surface of the second wafer;

forming a layer of bonding material on the front surface of the second wafer, the studs projecting vertically therefrom;

aligning the stud to the opening in the back surface of the first wafer; and

bonding the second wafer to the first wafer using the layer of bonding material, so that the stud makes electrical contact with the via, further comprising the steps of;

forming a via in the second wafer extending from the front surface thereof, the via being characterized by a lateral dimension at the front surface;

removing material from the second wafer at the back surface thereof;

forming an opening in the back surface of the second wafer, thereby exposing the via therein, said opening having a lateral dimension greater than said lateral dimension of the via;

forming a layer of conducting material in said opening;

providing a third wafer having a front surface, the third wafer having devices formed therein adjacent to the front surface thereof;

forming a stud on the front surface of the third wafer;

forming a layer of bonding material on the front surface of the third wafer, the studs projecting vertically therefrom;

aligning the stud to the opening in the back surface of the second wafer; and

bonding the third wafer to the second wafer using the layer of bonding material, so that the stud of the third wafer makes electrical contact with the via of the second wafer, with the stud of the second wafer, and with the via of the first wafer.

2. A method according to 1, wherein said step of removing material causes the wafer to have a thickness of less than 20 μ

m.

3. A method according to claim 1, further comprising the step of attaching a handling plate to the front surface of the first wafer using a layer of bonding material.

4. A method according to claim 1, further comprising the step of forming a conducting body in one of the first wafer and the second wafer and connecting to the via in the first wafer, the conducting body extending laterally under the devices of the first wafer, and wherein the opening in the back side of the first wafer is separated laterally from the via in accordance with the lateral extent of the conducting body.

5. A method according to claim 1, further comprising the steps of:

forming an additional opening in the back surface of the first wafer;

forming an additional layer of conducting material in said additional opening;

forming an additional stud on the front surface of the second wafer; and

aligning the additional stud to the additional opening in the back surface of the first wafer; and

wherein said step of bonding the second wafer to the first wafer forms a connection between the additional stud and the additional layer of conducting material for conducting heat between the second wafer and the first wafer.

6. A method according to claim 5, wherein the additional layer of conducting material is electrically insulated from the via.

7. A method according to claim 1, further comprising the steps of:

forming an additional opening in the back surface of the second wafer;

forming an additional layer of conducting material in said additional opening;

forming an additional stud on the front surface of the third wafer; and

aligning the additional stud to the additional opening in the back surface of the second wafer;

and wherein said step of bonding the third wafer to the second wafer forms a connection between the additional stud and the additional layer of conducting material for conducting heat between the third wafer and the second wafer.

8. A method according to claim 1, wherein said bonding material is a thermoplastic material.

9. A method according to claim 8, wherein the thermoplastic material is polyimide.

10. A method according to claim 1, further comprising the step of attaching the three-dimensional integrated device to a multichip module.

11. A method according to claim 1, further comprising the step of attaching the three-dimensional integrated device to an insulating layer having wiring formed therein using a stud-via connection.

12. A method according to claim 1, wherein the first wafer and second wafer have cache memory devices, and the third wafer has logic devices.

13. A method according to claim 1, wherein at least one of the first wafer, the second wafer and the third wafer includes a MEMS device.