Memory circuit with supply voltage flexibility and supply voltage adapted performance

• US 7,355,915 B2
• Filed: 08/24/2005
• Issued: 04/08/2008
• Est. Priority Date: 08/24/2004
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Coste, Jean-Patrice, Gouin, Vincent, Chanussot, Christophe
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US11/212,082
• Publication Number:
  US 20060050572A1
• Time in Patent Office: 958 Days
• Field of Search: 365/210, 365/189.08, 365/230.06, 365/226, 365/205, 365/207, 365/208, 365/185.2, 365/194
• US Class Current: 365/210.1
• CPC Class Codes: G11C 2207/065 Sense amplifier drivers
• CPC Class Codes: G11C 2207/2227 Standby or low power modes
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

The inventive memory circuit comprises a plurality of memory cells. The memory circuit further comprises a memory access means being controlled by at least one control signal. In addition, a control means for generating the at least one control signal is contained in the memory circuit, with the control means comprising a delay means. The delay means delays a switching of the at least one control signal. The delay time is adjustable in view of the applied supply voltage.

Claims

1. A memory circuit comprising:

a plurality of memory cells organized in rows and columns;

memory access circuitry controlled by at least one control signal; and

control circuitry for generating the at least one control signal comprising;

delay circuitry which delays a switching of the at least one control signal with a respective delay time being adjustable in view of an applied supply voltage, wherein

the memory access circuitry supports a memory read access mode and a memory write access mode; and

the delay time is independently selectable for the memory read access mode and for the memory write access mode.

2. The memory circuit of claim 1, wherein:

the memory circuit comprises a plurality of bit lines each coupled to a column of the plurality of memory cells; and

the delay circuitry comprises;

a dummy bit line coupled to dummy memory cells, wherein a signal transmission behavior of the dummy bit line is characteristic of a signal transmission behavior of the bit lines, and wherein the at least one control signal is generated using a signal on the dummy bit line; and

a driver unit driving the dummy bit line, wherein the driver discharges the dummy bit line.

3. The memory circuit of claim 2, wherein a driving capability of the driver unit is independently selectable for at least two different supply voltage operating modes of the memory circuit, wherein the supply voltage operating modes include a high supply voltage mode and a low supply voltage mode, and wherein the driving capability for the high supply voltage mode is higher than the driving capability for the low supply voltage mode.

4. A memory circuit comprising:

a plurality of memory cells organized in rows and columns;

a plurality of bit lines each coupled to a column of the plurality of memory cells;

memory access circuitry controlled by at least one control signal; and

control circuitry for generating the at least one control signal comprising;

delay circuitry which delays a switching of the at least one control signal with a respective delay time being adjustable in view of an applied supply voltage, wherein the delay circuitry comprises;

a dummy bit line coupled to dummy memory cells, wherein a signal transmission behavior of the dummy bit line is characteristic of a signal transmission behavior of the bit lines, and wherein the at least one control signal is generated using the signal on the dummy bit line; and

a driver unit driving the dummy bit line, wherein the driver discharges the dummy bit line, wherein a driving capability of the driver unit is independently selectable for at least two different supply voltage operating modes of the memory circuit, wherein the supply voltage operating modes include a high supply voltage mode and a low supply voltage mode, and wherein the driving capability for the high supply voltage mode is higher than the driving capability for the low supply voltage mode.

5. The memory circuit of claim 4, wherein the driver unit comprises:

a first MOS driver transistor actively driving the dummy bit line in the low supply voltage mode;

a second MOS driver transistor actively driving the dummy bit line in the high supply voltage mode, wherein a transistor width of the second driver transistor is i times higher than the transistor width of the first driver transistor, where i>

1 and wherein i is a natural number.

6. The memory circuit of claim 4, wherein the driving capability of the driver unit is independently selectable for a memory read access mode and for the memory write access mode via a second pin.