Apparatus and methods for communicating with programmable logic devices

• US 7,356,620 B2
• Filed: 06/10/2003
• Issued: 04/08/2008
• Est. Priority Date: 06/10/2003
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Duwel, Keith, Veenstra, Kerry, Prasad, Nitin, Joyce, Juju Chacko, Xia, Renxin
• Primary Examiner(s): SHIN, CHRISTOPHER B
• Application Number:
  US10/457,874
• Publication Number:
  US 20060038586A1
• Time in Patent Office: 1,764 Days
• Field of Search: 714/725, 713/1, 365/63, 365/159.07, 365/238.5, 365/185.23, 341/55, 341/100, 326/40, 348/211.99, 710 8- 14, 716/16
• US Class Current: 710/8
• CPC Class Codes: G06F 13/10 Program control for peripheral devices G06F13/14 - G06F13/42 take precedence
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: H03K 19/1776 for memories

Abstract

A circuit arrangement includes a programmable logic device. The programmable logic device includes configuration logic circuitry. The programmable logic device also includes configurable interconnects. The circuit arrangement further includes a storage device configured to provide data to the programmable logic device. The storage device communicates with the programmable logic device via a bi-directional interface.

Claims

1. An integrated circuit comprising:

a plurality of programmable logic elements, configurable to implement user-defined logic functions;

a serial memory interface coupled to the plurality of programmable logic elements and comprising;

a data output for serially providing data to a memory device;

a data input for serially receiving data from the memory device;

the received data comprising a configuration bitstream;

a clock output for providing a clock signal to the memory device; and

a chip enable output; and

a configuration circuit to receive the configuration bitstream and configure the plurality of programmable logic elements.

2. The integrated circuit of claim 1 wherein the memory interface further comprises:

a read/busy input for receiving a signal from the memory device indicating the availability of the memory device.

3. The integrated circuit of claim 2 further comprising:

a reset output for providing a reset signal to the memory device.

4. The integrated circuit of claim 1 wherein the data output further provides operation codes to the memory device.

5. The integrated circuit of claim 1 wherein the memory interface is a serial-peripheral interface.

6. The integrated circuit of claim 1 wherein when the configuration bitstream is received by the memory interface, the integrated circuit acts as a master device.

7. The integrated circuit of claim 1 wherein the memory device is a FLASH PROM.

8. The integrated circuit of claim 1 wherein the chip enable output provides a signal to select or deselect the memory device.

9. The integrated circuit of claim 1 wherein the chip enable output provides a signal to enable or disable the memory device.

10. The integrated circuit of claim 1 wherein the integrated circuit is a field programmable gate array.

11. A method of configuring an integrated circuit comprising:

with a serial memory interface on the integrated circuit,

providing a clock signal to a memory device;

providing a chip enable signal to the memory device;

serially providing an operation code to the memory device, the operation code instructing the memory device to provide a configuration bitstream; and

serially receiving the configuration bitstream; and

with a configuration circuit, configuring the integrated circuit.

12. The method of claim 11 wherein the operation code is provided using a data output.

13. The method of claim 11 wherein the memory device is a FLASH PROM.

14. The integrated circuit of claim 11 wherein the integrated circuit is a field programmable gate array.

15. The method of claim 11 wherein the memory interface comprises a serial-peripheral interface.

16. The method claim 11 further comprising:

providing data to the memory device using the data output; and

storing the data in the memory device.

17. The method of claim 16 further comprising:

reading the data from the memory device using the data input.