Plasma treatment at film layer to reduce sheet resistance and to improve via contact resistance
First Claim
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1. A semiconductor device, comprising:
- a substrate;
a plurality of logic devices located over the substrate;
an insulating layer located over the plurality of logic devices and including a plurality of recesses exposing underlying ones of the plurality of logic devices;
an agglutinating layer located over the insulating layer including within the plurality of recesses, the agglutinating layer having an enlarged grain size due to plasma treatment with a process chemistry comprising nitrogen and hydrogen;
a barrier layer located over the plasma-treated agglutinating layer including within the plurality of recesses; and
a conductive layer located over the barrier layer including within the plurality of recesses.
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Abstract
A method of manufacturing a semiconductor device contact including forming an insulating layer over a substrate and forming an agglutinating layer over the insulating layer. The agglutinating layer is then exposed to a plasma treatment. A barrier layer is formed over the plasma-treated agglutinating layer, and a conductive layer is formed over the barrier layer.
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Citations
20 Claims
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1. A semiconductor device, comprising:
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a substrate; a plurality of logic devices located over the substrate; an insulating layer located over the plurality of logic devices and including a plurality of recesses exposing underlying ones of the plurality of logic devices; an agglutinating layer located over the insulating layer including within the plurality of recesses, the agglutinating layer having an enlarged grain size due to plasma treatment with a process chemistry comprising nitrogen and hydrogen; a barrier layer located over the plasma-treated agglutinating layer including within the plurality of recesses; and a conductive layer located over the barrier layer including within the plurality of recesses. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A semiconductor device, comprising:
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a logic device located over a substrate; an insulating layer located over the logic device, wherein a recess in the insulating layer exposes at least a portion of the logic device; an agglutinating layer located over the insulating layer and within the recess, the agglutinating layer having an enlarged grain size due to plasma treatment, wherein the enlarged grain size of the plasma-treated agglutinating layer is about 20% larger than prior to plasma treatment; a barrier layer located over the plasma-treated agglutinating layer and within the recess; and a conductive layer located over the barrier layer and within the recess. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A semiconductor device, comprising:
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a logic device located over a substrate; an insulating layer located over the logic device and having a recess that exposes at least a portion of the logic device; and a contact located within the recess and comprising; an agglutinating layer having an enlarged grain size due to plasma treatment; a barrier layer located over the plasma-treated agglutinating layer; and a conductive layer located over the barrier layer; wherein the contact has at least one of; a sheet resistance ranging between about 70 Ω
/nm2 and about 130 Ω
/nm2; anda contact resistance ranging between about 6 Ω
/nm2 and about 9 Ω
/nm2.
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Specification
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Current AssigneeTaiwan Semiconductor Manufacturing Company Limited
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Original AssigneeTaiwan Semiconductor Manufacturing Company Limited
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InventorsZhang, Wei, Chou, Yu-Hua, Tseng, Chi-Chan, Luo, Tzo-Hung, Yang, Jong-Chen, Tsai, Jian-Shin
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Primary Examiner(s)Nhu; David
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Application NumberUS11/419,537Publication NumberTime in Patent Office694 DaysField of Search257/774, 257/127, 257/69, 257/288, 257/396, 257/204, 257/761, 257/763, 257/622US Class Current257/774CPC Class CodesH01L 21/76843 formed in openings in a die...H01L 21/7685 the layer covering a conduc...H01L 21/76856 by treatment in plasmas or ...H01L 21/76862 Bombardment with particles,...
