Method and system for terminating write commands in a hub-based memory system

• US 7,363,419 B2
• Filed: 05/28/2004
• Issued: 04/22/2008
• Est. Priority Date: 05/28/2004
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Larson, Douglas A., Cronin, Jeffrey J.
• Primary Examiner(s): Sparks; Donald
• Assistant Examiner(s): VO, THANH DUC
• Application Number:
  US10/857,467
• Publication Number:
  US 20050268060A1
• Time in Patent Office: 1,425 Days
• Field of Search: None
• US Class Current: 711/5
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 13/423 with synchronous protocol
• CPC Class Codes: G06F 13/4256 using a clocked protocol

Abstract

A memory hub receives downstream memory commands and processes each received downstream memory command to determine whether the memory command includes a write command directed to the memory hub. The memory hub operates in a first mode when the write command is directed to the hub to develop memory access signals adapted to be applied to memory devices. The memory hub operates in a second mode when the write command is not directed to the hub to provide the command'"'"'s write data on a downstream output port adapted to be coupled to a downstream memory hub.

Claims

1. A method of processing write commands in a memory system having a memory hub architecture including a plurality of memory hubs coupled in a point-to-point architecture beginning with a first hub and ending with a last hub, the method comprising:

applying a read command to the first hub in the system;

subsequent to applying the read command, applying a write command to the first hub in the system directed to a hub upstream from the hub to which the read command is directed, a time interval is defined between when the read and write commands are applied, the time interval is a function of the position of the downstream hub to which the read command is directed relative to the upstream hub to which the write command is directed;

determining in the first hub whether the write command is directed to that hub;

when the determination indicates the write command is directed to the first hub, terminating downstream forwarding of the write data;

when the determination indicates the write command is not directed to the first hub, forwarding the write data downstream to a second hub; and

repeating the operations of determining through when the determination indicates the write command is not directed for all required memory hubs.

2. The method of claim 1 wherein the memory system includes a series of memory hubs in addition to the first and second hubs, and wherein the method further comprises repeating the acts of claim 1 except for the act of applying a write command to a first hub in the system for each of the memory hubs in the series.

3. The method of claim 2, further comprising forwarding the write command beyond a memory hub in which downstream forwarding of the write data is terminated until the write command reaches a final memory hub in the series of memory hubs.

4. The method of claim 1 wherein the write command includes a command portion and a write data portion, and wherein terminating downstream forwarding of the command comprises terminating the forwarding of both the command portion and write data portion.

5. A method of operating a system memory having a memory hub architecture, the system memory including a plurality of memory modules coupled in series beginning with a first memory module and ending with a last memory module, each memory module including a memory hub, and the method comprising:

applying a read command to the first memory module;

detecting in each memory hub whether a write command applied subsequent to the read command is directed to the corresponding memory module, a time interval is defined between when the read and Write commands are applied, the time interval is a function of the position of the memory module to which the read command is directed relative to the memory module to which the write command is directed;

when the operation of detecting indicates the write command is directed to the corresponding module, terminating the forwarding of the write data to downstream memory modules.

6. The method of claim 5 wherein detecting comprises comparing an address component of the write command to an address associated the memory module.

7. The method of claim 5 wherein the write command includes a command portion and a write data portion, and wherein terminating the forwarding of the write data to downstream memory modules comprises terminating the forwarding of write data portion.

8. A memory system, comprising:

a system controller; and

a plurality of memory modules, each memory module being coupled to adjacent memory modules through respective high-speed communications links, at least one of the memory modules being coupled to the system controller through a respective high-speed communications link, and each memory module comprising;

a plurality of memory devices; and

a memory hub coupled to the memory devices and including a downstream input port adapted to receive downstream memory requests, and the hub operable to process each received downstream memory request to determine whether the memory request includes a write command directed to the memory module, and the memory hub operable in a first mode when the write command is directed to the module to apply memory access signals to the memory devices, and the hub operable in a second mode when the write command is not directed to the module to provide the command on a downstream output port,

the system controller configured to determine a timing between when the system controller applies a read command to a first memory module relative to when the system controller applies a write command to a second module that is upstream of the first module as a function of the position of the downstream module to which the read command is directed relative to the upstream module to which the write command is directed each memory hub except a last memory hub adapted to receive upstream memory responses from an adjacent downstream module and provide such responses to an adjacent upstream memory module.

9. The memory system of claim 8 wherein the system controller comprises a memory controller.

10. The memory system of claim 8 wherein the time between when the read and write commands increase the farther downstream is the downstream module relative to the upstream module.

11. The memory system of claim 8 wherein the memory devices comprise dynamic random access memory devices.

12. The memory system of claim 8 wherein the write command comprises a command portion and a data portion.

13. The memory system of claim 8 wherein the downstream memory request includes an address portion, and wherein each memory hub determines whether the write command is directed to the memory by comparing a value of the address portion to an address associated with the memory module.

14. The memory system of claim 8 wherein the memory access signals comprise address, control, and data signals.

15. The memory system of claim 8 wherein the hub is operable in the second mode to provide received write data on a downstream data port adapted to be coupled to a downstream memory hub.

16. The memory system of claim 15 wherein the memory hub is operable in the first mode to provide the command on the downstream output port and to terminate providing received write data on the downstream data port.

17. The memory system of claim 8 wherein each memory hub except a last memory hub adapted to receive upstream memory responses from an adjacent downstream module and provide such responses to an adjacent upstream memory module.

18. A computer system, comprising:

a processor;

a system controller coupled to the processor;

an input device coupled to the processor through the system controller;

an output device coupled to the processor through the system controller;

a storage device coupled to the processor through the system controller; and

a plurality of memory modules coupled to the system controller, each memory module being coupled to adjacent memory modules through respective high-speed communications links, at least one of the memory modules being coupled to the system controller through a respective high-speed communications link, and each memory module comprising;

a plurality of memory devices; and

a memory hub coupled to the memory devices and including a downstream input port adapted to receive downstream memory requests, and the hub operable to process each received downstream memory request to determine whether the memory request includes a write command directed to the memory module, and the memory hub operable in a first mode when the write command is directed to the module to apply memory access signals to the memory devices, and the hub operable in a second mode when the write command is not directed to the module to provide the command on a downstream output port,

the system controller configured to determine a timing between when the system controller applies a read command to a first memory module relative to when the system controller applies a write command to a second module that is upstream of the first module as a function of the position of the downstream module to which the read command is directed relative to the upstream module to which the write command is directed each memory hub except a last memory hub adapted to receive upstream memory responses from an adjacent downstream module and provide such responses to an adjacent upstream memory module.

19. The computer system of claim 18 wherein each high-speed communications link comprises an optical link.

20. The computer system of claim 18 wherein the time between when the read and write commands increase the farther downstream is the downstream module relative to the upstream module.

21. The computer system of claim 18 wherein the memory devices comprise dynamic random access memory devices.

22. The computer system of claim 18 wherein the write command comprises a command portion and a data portion.

23. The computer system of claim 18 wherein the downstream memory request includes an address portion, and wherein each memory hub determines whether the write command is directed to the memory by comparing a value of the address portion to an address associated with the memory module.

24. The computer system of claim 18 wherein the processor comprises a central processing unit (“

CPU”

).

25. The computer system of claim 18 wherein each memory hub except a last memory hub adapted to receive upstream memory responses from an adjacent downstream module and provide such responses to an adjacent upstream memory module.