Optimizing write/erase operations in memory devices

• US 7,363,421 B2
• Filed: 01/13/2005
• Issued: 04/22/2008
• Est. Priority Date: 01/13/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Intini, Agata, Di Sena, Angelo
• Primary Examiner(s): Thai; Tuan V.
• Application Number:
  US11/035,013
• Publication Number:
  US 20060155917A1
• Time in Patent Office: 1,195 Days
• Field of Search: 711/103, 711/100, 711/104, 711/105, 711/154, 711/156, 365/185.29
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles

Abstract

A method controls write/erase operations in a memory device including memory blocks that are exposed to wear as a result of repeated erasures. The method includes: storing the erase counts of the memory blocks, creating a chain storing the erase counts of the memory blocks that are available for writing at a certain instant of time, and selecting for writing, out of the blocks in the memory device available for writing, the block having the lowest erase count in the chain.

Claims

1. A method of controlling write/erase operations in a memory device including memory blocks, said blocks being exposed to wear as a result of repeated erasures, the method comprising:

arranging the blocks in the memory device in orderly logical positions;

storing erase counts associated with the memory blocks in a table, entering as an i-th entry in the table a number of erasures performed on a block in an i-th position in the memory device;

creating a chain storing block numbers and corresponding erase counts for memory blocks that are available for writing at a certain instant of time;

selecting for writing, out of the blocks of said memory device available for writing, the block having the lowest erase count in said chain; and

writing data in said block having the lowest erase count in said chain.

2. The method of claim 1, including the step of:

updating the chain.

3. The method of claim 1, including the steps of associating said memory device with a RAM memory and creating said chain in a portion of said RAM memory.

4. The method of claim 1, wherein each block is partitioned into a main area and a spare area, and the table is located in the main area of one of said blocks.

5. The method of claim 4, including the steps of providing pages for storing table entries of said table, wherein said pages contain a flag in said spare area of the one of said blocks.

6. The method of claim 1, further comprising providing pages for storing table entries of said table, wherein said pages contain a flag indicating that the pages store said table entries.

7. The method of claim 6, including the step of searching for said table within said memory device during power-on operation by recognizing the pages storing said table entries based on said flag.

8. The method of claim 7, including the step of searching said table within said memory device starting from the last physical block in said memory device.

9. The method of claim 1, including the steps of:

selecting a last non-defective physical memory block in said memory device; and

writing said table in said non-defective memory block when said memory device is formatted for the first time.

10. The method of claim 9, wherein for each subsequent formatting operation of said memory device said table is updated by incrementing the erase counts of the memory blocks that will be erased.

11. The method of claim 1 wherein creating said chain comprises storing for each said block available for writing:

a block number;

an associated erase count; and

a pointer to a subsequent element in the chain.

12. The method of claim 11, wherein said chain is ordered in a FIFO (First In First Out) way.

13. The method of claim 11, including the step of reconstructing said chain at every device power-on.

14. The method of claim 1, including the steps of:

associating with said memory device a RAM memory;

detecting when the erase count for a given block value reaches a maximum storable value;

loading said erase counts in said RAM memory;

dividing by two said erase counts stored in said RAM memory; and

re-writing said divided erase counts in said memory device.

15. The method of claim 1, including the step of selecting said memory device as a flash memory device.

16. A method of controlling write/erase operations in a memory device including memory blocks, said blocks being exposed to wear as a result of repeated erasures, the method comprising:

storing erase counts of said memory blocks, each erase count reflecting the number of erasures of an associated one of the memory blocks;

creating a chain storing block numbers and corresponding erase counts for memory blocks that are available for writing at a certain instant of time, wherein creating the chain comprises storing for each said block available for writing;

a block number;

an associated erase count; and

a pointer to a subsequent element in the chain;

selecting for writing, out of the blocks of said memory device available for writing, the block having the lowest erase count in said chain; and

writing data in said block having the lowest erase count in said chain, wherein creating said chain comprises performing, for each said block available for writing, the operations of;

reading an associated erase count;

creating a corresponding element for said chain including a block number and said erase count previously read; and

inserting the element thus created in said chain.

17. A computer system, comprising:

a memory device including memory blocks that are exposed to wear as a result of repeated erasures;

storing means for storing erase counts of the memory blocks, each erase count reflecting the number of erasures of an associated one of the memory blocks;

means for creating a chain storing block numbers and corresponding erase counts of the memory blocks that are available for writing at a certain instant of time; and

means for selecting for writing, out of the blocks of the memory device available for writing, the block having the lowest erase count in the chain, wherein the means for creating the chain include means for;

accessing each block of the memory device that is available for writing;

reading from the storing means the erase count associated with the block;

creating a corresponding element for the chain including a block number and the erase count previously read; and

inserting the element thus created in the chain.

18. The system of claim 17, further comprising:

means for removing an element of the chain corresponding to the block having the lowest erase count in the chain after the block is selected for writing.

19. The system of claim 17 wherein the means for storing the erase counts store the erase count of each block in a table in a last non-defective memory block in the memory device.

20. The system of claim 17 wherein the means for creating the chain include means for storing, for each the block available for writing, a chain element that includes:

a block number of the block;

the erase count of the block; and

a pointer to a subsequent element in the chain.

21. The system of claim 17, wherein the chain is ordered in a FIFO (First In First Out) way.

22. The system of claim 17 wherein the means for creating include means for reconstructing the chain at every device power-on.

23. The system of claim 17, further comprising:

a RAM memory;

means for detecting when the erase count for a given block value reaches a maximum storable value;

means for loading the erase counts in the RAM memory;

means for dividing by two the erase counts stored in the RAM memory; and

means for writing the divided erase counts in the memory device.

24. A computer product for controlling write/erase operations in a memory device including memory blocks that are exposed to wear as a result of repeated erasures, the computer product being loadable into a memory of a digital computer and comprising instruction code portions for performing, when the product is run on a computer, the following operations:

storing erase counts of the memory blocks, each erase count reflecting the number of erasures of an associated one of the memory blocks;

creating a chain storing block numbers and corresponding erase counts of the memory blocks that are available for writing at a certain instant of time; and

selecting for writing, out of the blocks of the memory device available for writing, the block having the lowest erase count in the chain, wherein creating the chain comprising performing, for each the block available for writing, the operations of;

reading an associated erase count;

creating a corresponding element for the chain including a block number and the erase count previously read; and

inserting the element thus created in the chain.

25. The computer product of claim 24, further including instruction code portions for performing, when the product is run on a computer, the following operations:

writing data in the block having the lowest erase count in the chain; and

updating the chain.

26. The computer product of claim 24, further including instruction code portions for performing, when the product is run on a computer, the following operations:

storing the erase count of each block in a table in a selected block of the memory device;

storing in the selected block a flag indicating that the table is stored in the selected block.

27. The computer product of claim 24, further including instruction code portions for performing, when the product is run on a computer, the following operation:

creating the chain by storing, for each the block available for writing;

a block number, an associated erase count, and a pointer to a subsequent element in the chain.

28. The computer product of claim 24, further including instruction code portions for performing, when the product is run on a computer, the following operations:

associating with the memory device a RAM memory;

detecting when the erase count for a given block value reaches a maximum storable value;

loading the erase counts in the RAM memory;

dividing by two the erase counts stored in the RAM memory; and

re-writing the divided erase counts in the memory device.

29. A system comprising:

a plurality of memory blocks arranged in orderly logical positions and that are exposed to wear as a result of repeated erasures; and

a processing unit configured to;

store erase counts for the memory blocks in the plurality of memory blocks in a table, entering an erase count for a respective block in a corresponding position in the table;

create a chain storing block numbers and corresponding erase counts for memory blocks in the plurality of memory blocks that are available for writing; and

select a memory block in the chain having a lowest erase count.

30. The system of claim 29 wherein the processing unit is further configured to selectively update the chain.

31. The system of claim 29, further comprising a RAM memory wherein the processing unit is configured to store the chain in the RAM memory.