Heterogeneous multiprocessor system and OS configuration method thereof
First Claim
1. A heterogeneous multiprocessor system including at least first and second processors and one or a plurality of interrupt controllers, said system comprising:
- first means which accepts an interrupt in each processor;
second means which inquires said accepted interrupt of an interrupt destination management table to select an interrupt destination processor;
third means which queues said accepted interrupt;
fourth means which generates an interprocessor interrupt to said selected interrupt destination processor;
fifth means which receives said interprocessor interrupt in said interrupt destination processor;
sixth means which performs interrupt process of the interrupt source processor in said interrupt destination processor;
seventh means which generates said interprocessor interrupt to said interrupt source processor in said interrupt destination processor;
eighth means which performs an interrupt end process in said interrupt source processor; and
ninth means which performs interrupt process in its own processor when said interrupt destination processor selected as a result of the inquiry to said interrupt destination management table is its own processor.
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Abstract
Interrupt process generated in a processor for arithmetic operation is offloaded onto a system control processor, thereby reducing disturbance to the processor for arithmetic operation. A heterogeneous multiprocessor system includes: means which accepts an interrupt in each CPU; means which inquires the accepted interrupt of an interrupt destination management table to select an interrupt destination CPU; means which queues the accepted interrupt; means which generates an inter-CPU interrupt to the selected interrupt destination CPU; each means which receives the inter-CPU interrupt in the interrupt source CPU, performs interrupt process of the interrupt source CPU, and generates the inter-CPU interrupt to the interrupt source CPU in the interrupt destination CPU; means which performs an interrupt end process; and means which performs interrupt process in its own CPU when the interrupt destination CPU selected as a result of the inquiry to the interrupt destination management table is its own CPU.
25 Citations
14 Claims
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1. A heterogeneous multiprocessor system including at least first and second processors and one or a plurality of interrupt controllers, said system comprising:
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first means which accepts an interrupt in each processor; second means which inquires said accepted interrupt of an interrupt destination management table to select an interrupt destination processor; third means which queues said accepted interrupt; fourth means which generates an interprocessor interrupt to said selected interrupt destination processor; fifth means which receives said interprocessor interrupt in said interrupt destination processor; sixth means which performs interrupt process of the interrupt source processor in said interrupt destination processor; seventh means which generates said interprocessor interrupt to said interrupt source processor in said interrupt destination processor; eighth means which performs an interrupt end process in said interrupt source processor; and ninth means which performs interrupt process in its own processor when said interrupt destination processor selected as a result of the inquiry to said interrupt destination management table is its own processor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. An OS configuration method for a heterogeneous multiprocessor system including at least first and second processors and one or a plurality of interrupt controllers, said method comprising:
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a first step of accepting an interrupt in an interrupt source processor; a second step of generating interrupt information; a third step of determining an interrupt destination processor of the accepted interrupt by the inquiry to an interrupt destination management table in said interrupt source processor; a fourth step of registering said interrupt information to an interrupt queue when said interrupt destination processor is its own processor, setting said interrupt information as “
under interrupt process” and
performing an interrupt process in its own processor if the interrupt is possible as a result of the comparison with a current mask level, and returning to a process before the interrupt if the interrupt is not possible as a result of the comparison with the current mask level; anda fifth step of, if said interrupt destination processor is a processor other than its own processor and an end process is required, setting a flag waiting for an end interrupt in said interrupt information, registering said interrupt information in the interrupt queue, generating an interprocessor interrupt in said interrupt destination processor, and returning to the process before interrupt. - View Dependent Claims (12, 13, 14)
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Specification