Method of fabricating a gate structure of a field effect transistor having a metal-containing gate electrode

• US 7,368,392 B2
• Filed: 04/23/2004
• Issued: 05/06/2008
• Est. Priority Date: 07/10/2003
• Status: Expired due to Fees

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Yi, Sang, Choi, Jinhan, Deshmukh, Shashank, Lee, Kyeong-Tae
• Primary Examiner(s): Vinh; Lan
• Assistant Examiner(s): ANGADI, MAKI A
• Application Number:
  US10/831,406
• Publication Number:
  US 20050009358A1
• Time in Patent Office: 1,474 Days
• Field of Search: 438/706, 257/412, 257/750
• US Class Current: 438/706
• CPC Class Codes: H01L 21/28035 the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities H01L21/28105 takes precedence
• CPC Class Codes: H01L 21/28123 Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
• CPC Class Codes: H01L 21/32136 using plasmas
• CPC Class Codes: H01L 21/32137 of silicon-containing layers
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: Y10S 438/942 Masking

Abstract

A method of etching metals and/or metal-containing compounds using a plasma comprising a bromine-containing gas. In one embodiment, the method is used during fabrication of a gate structure of a field effect transistor having a titanium nitride gate electrode, an ultra-thin (about 10 to 20 Angstroms) silicon dioxide gate dielectric, and a polysilicon upper contact. In a further embodiment, the gate electrode is selectively notched to a pre-determined width.

Claims

1. A method for fabricating a gate structure of a field effect transistor, comprising:

(a) providing a substrate having a metal-containing gate electrode layer formed upon a gate dielectric layer, a contact layer formed upon the metal-containing gate electrode layer, and a patterned mask formed upon the contact layer, the patterned mask defining location and topographic dimensions of the gate structure;

(b) etching the contact layer through the patterned mask, the step of etching causing a residue to be deposited upon sidewalls of the contact layer and a lower surface of the feature being etched;

(c) etching the metal-containing gate electrode layer using a plasma comprising a bromine-containing gas, wherein the residue on the sidewalls is used to protect the sidewalls of the contact layer from undercutting, wherein said etching further comprises a soft landing period and an overetch period following the soft landing period, where each of the periods uses different process time and substrate bias power; and

(d) etching the gate dielectric layer.

2. The method of claim 1 wherein the metal-containing gate electrode layer comprises at least one of Ti, Ta, W, TiN, TaN, and WN.

3. The method of claim 1 wherein the gate dielectric layer comprises at least one of SiO₂, SiON, HfO₂, HfSiO₂, and HfSiON.

4. The method of claim 1 wherein the bromine-containing gas comprises at least one of HBr and Br₂.

5. The method of claim 1 wherein the plasma further comprises at least one of Cl₂, O₂, helium-oxygen (He—

O₂), N₂, Ar, Ne, and He.

6. The method of claim 5 wherein the step (c) further comprises:

providing HBr and Cl₂ at a HBr;

Cl₂ flow ratio in a range from 1;

8 to 1;

0 during the soft landing etch period.

7. The method of claim 5 wherein the step (c) further comprises:

providing HBr and Cl₂ at a HBr;

Cl₂ flow ratio in a range from 1;

8 to about 1;

0;

maintaining the substrate at a temperature of about 20 to 90 degrees Celsius;

applying power to an inductively coupled antenna between about 300 and 3000 W;

applying a substrate bias power between about 0 and 300 W; and

maintaining a chamber pressure between about 4 and 80 mTorr.

8. The method of claim 1 wherein the step (c) further comprises laterally etching a metal-containing gate electrode of the gate structure to a pre-determined width using no substrate bias power.

9. The method of claim 8 wherein the step of laterally etching is performed after the soft landing period.

10. The method of claim 8 wherein the step of laterally etching is performed after the overetch period.

11. The method of claim 1 wherein the contact layer comprises polysilicon (Si).

12. The method of claim 11 wherein the contact layer is etched using a plasma comprising Cl₂, HBr, and a fluorine-containing gas.

13. The method of claim 12 wherein the fluorine-containing gas comprises at least one of CF₄ and NF₃.

14. The method of claim 12 wherein the plasma further comprises at least one of N₂, helium-oxygen (He—

O₂), Ar, and Ne.

15. The method of claim 12 further comprising:

providing HBr and Cl₂ at a HBr;

Cl₂ flow ratio ranging from 1;

15 to 15;

1; and

providing HBr and CF₄ at a HBr;

CF₄ flow ratio ranging from 1;

5 to about 1;

0.

16. The method of claim 14 further comprising:

providing HBr and Cl₂ at a HBr;

Cl₂ flow ratio ranging from 1;

15 to 15;

1;

providing HBr and CF₄ at a HBr;

CF₄ flow ratio ranging from 1;

5 to about 1;

0;

maintaining the substrate at a temperature of about 20 to 90 degrees Celsius;

applying power to an inductively coupled antenna between about 300 and 3000 W;

applying a substrate bias power between about 0 and 300 W; and

maintaining a chamber pressure between about 4 and 80 mTorr.

17. The method of claim 12 wherein the step of etching the contact layer further comprises:

providing the fluorine-containing gas during a main etch period; and

terminating the flow of the fluorine-containing gas during a soft landing period.

18. The method of claim 17 wherein the step of etching the contact layer further comprises an overetch period performed after the soft landing period, wherein the overetch period has a different process time, flow of the fluorine-containing gas, and flow of Cl₂ relative to the soft landing period.

19. The method of claim 18 wherein, during the overetch period, the flow of the fluorine-containing gas and the flow of Cl₂ are terminated.

20. The method of claim 12 further comprising:

removing post-etch residue from the lower surface using a plasma comprising at least one of Ar and Ne.

21. The method of claim 20 wherein the plasma further comprises at least one of Cl₂ and HBr.

22. The method of claim 21 further comprising:

providing Ar and HBr at an Ar;

HBr flow ratio ranging from 1;

20 to about 1;

0.

23. The method of claim 1 wherein the step (d) uses a plasma comprising at least one of CF₄ and CHF₃.

24. The method of claim 1 wherein the step (d) uses a plasma comprising at least one of Cl₂ and CO.

25. The method of claim 1 wherein the patterned mask comprises at least one of SiO₂, SiON, HfO₂, Si₃N₄, HfSiO₂, and HfSiON.

26. The method of claim 1 wherein the step (d) further comprises:

removing the patterned mask after etching the gate dielectric layer.

27. The method of claim 26 wherein the step (d) further comprises:

removing residue after removal of the patterned mask.

28. The method of claim 27 further comprising:

removing the patterned mask using at least one of a buffered oxide etch process and hot phosphoric acid.

29. The method of claim 1 wherein the steps (c) and (d) are performed in a single processing reactor.

41. The method of claim 1, wherein the etching of the contact layer comprises a selectivity for the contact layer over the mask layer of at least 80:

1 and a selectivity for the contact layer over the metal-containg gate electrode layer of at least 100;

1.

30. A method of etching a metal-containing layer, comprising:

providing a substrate having a metal-containing layer formed upon a high-k dielectric material; and

etching the metal-containing layer using a plasma comprising a bromine-containing gas and having a selectivity for the metal-containing layer over the high-k dielectric material of at least 100;

1, wherein the etching further comprises a soft landing period and an overetch period performed after the soft landing period, and wherein each of the periods uses different process time and substrate bias power.

31. The method of claim 30 wherein the metal-containing layer comprises at least one of Ti, Ta, W, TiN, TaN, and WN.

32. The method of claim 30 wherein the high-k dielectric material comprises at least one of HfO₂, HfSiO₂, and HfSiON.

33. The method of claim 30 wherein the bromine-containing gas comprises at least one of HBr and Br₂.

34. The method of claim 30 wherein the plasma further comprises at least one of Cl₂, O₂, helium-oxygen (He—

O₂), N₂, Ar, Ne, and He.

35. The method of claim 34 wherein the etching step further comprises:

providing HBr and Cl₂ at a HBr;

Cl₂ flow ratio in a range from 1;

8 to about 1;

0.

36. The method of claim 34 wherein the etching step further comprises:

providing HBr and Cl₂ at a HBr;

Cl₂ flow ratio in a range from 1;

8 to about 1;

0;

maintaining the substrate at a temperature of about 20 to 90 degrees Celsius;

applying power to an inductively coupled antenna between about 300 and 3000 W;

applying a substrate bias power between about 0 and 300 W; and

maintaining a chamber pressure between about 4 and 80 mTorr.

37. The method of claim 30 wherein the metal-containing layer is a patterned metal-containing layer.

38. The method of claim 37 wherein the etching step further comprises a notching period of laterally etching the metal-containing layer using no substrate bias power.

39. The method of claim 38 wherein the notching period is performed after one of the soft landing period or the overetch period.

40. A method for fabricating a gate structure of a field effect transistor, comprising:

(a) providing a substrate having a metal-containing gate electrode layer formed upon a gate dielectric layer and a contact layer formed upon the gate electrode layer;

(b) forming a patterned mask on the contact layer, the patterned mask defining location and topographic dimensions of the gate structure;

(c) etching the contact layer using a plasma comprising Cl₂, HBr, and a fluorine-containing gas, wherein the step of etching the contact layer comprises a main etch period for etching a bulk of the contact layer and a soft landing period for etching a remainder of the contact layer;

(d) etching the metal-containing gate electrode layer using a plasma comprising a bromine-containing gas; and

(e) etching the gate dielectric layer.