Monolithic GPS RF front end integrated circuit

• US 7,369,830 B2
• Filed: 09/13/2004
• Issued: 05/06/2008
• Est. Priority Date: 07/27/2000
• Status: Expired due to Fees

• Current Assignee: CSR Technology Incorporated (Qualcomm, Inc.)
• Original Assignee: SIRF Technology Incorporated (Qualcomm, Inc.)
• Inventors: Tso, Robert, McConnell, Richard Joseph
• Primary Examiner(s): Trinh; Sonny
• Application Number:
  US10/940,597
• Publication Number:
  US 20050096004A1
• Time in Patent Office: 1,331 Days
• Field of Search: 455/259, 455/269, 455/230, 455/150.1, 455/280, 455/323, 455/313, 455/334, 455/136, 455/138, 455/556.1, 455/245.1, 455/165.1, 455/183.1, 455/456.6, 375/316, 375/345
• US Class Current: 455/259
• CPC Class Codes: G01S 19/18 Military applications
• CPC Class Codes: G01S 19/36 relating to the receiver frond end
• CPC Class Codes: H04B 1/28 the receiver comprising at least one semiconductor device having three or more electrodes

Abstract

A highly integrated GPS RF Front End which uses a single conversion stage employs an image rejection mixer stage to eliminate the need for an image reject RF bandpass filter. Also a relatively high sample rate A/D is employed which allows a timeless monolitic IF Filter to be used. The disclosure also discusses a GPS Front End topology that is easily integrated from industry standard building blocks. With the broad variation in potential receiver designs, the present invention includes some specific receiver topologies that lend themselves to a high level of integration. The specific designs presented here are comprised of industry standard building blocks and functions that have been described elsewhere in the related art.

Claims

1. A highly integrated Global Positioning System (GPS) RF front end, comprising:

a Radio Frequency Integrated Circuit (RFIC) including;

a single stage downconverter using dual mixers;

an I/Q Intermediate Frequency (IF) active filter, coupled to the downconverter, wherein the IF active filter is selectively powered-on and powered-down within the RE front end;

an Automatic Gain Control (AGC) amplifier, coupled to the downconverter;

an Analog-to-Digital Converter (ADC), coupled to the AGC amplifier; and

a frequency synthesize section, wherein the noise bandwidth of the GPS RF front end is set by the IF active filter when the IF active filter is selective powered-on.

2. The GPS RF front end of claim 1, further comprising a Low Noise Amplifier (LNA) coupled to the I/Q Intermediate Frequency active filter.

3. The GPS RF front end of claim 1, wherein the outputs of the RFIC are Positive Emitter Collector Logic (PECL) compatible.

4. The GPS RF front end of claim 3, wherein the PECL compatible outputs of the RFIC include a SIGN output signal and a MAG output signal from the ADC.

5. The GPS RF front end of claim 4, wherein the PECL compatible outputs of the RFIC further include an acquisition clock (ACQCLK) signal generating by the frequency synthesizer section.

6. The GPS RF front end of claim 4, wherein the PECL compatible outputs further include GPS clock (GPSCLK) signal output from the frequency synthesizer section.

7. The GPS RF front end of claim 1, wherein the frequency synthesizer section further comprises:

a reference oscillator;

a frequency double, coupled to the reference oscillator;

a divide-by-9 circuit coupled to the frequency doubler;

a Phase and Frequency Detector (PFD), coupled to the divide-by-9 circuit;

a charge pump, coupled to the PFD;

a Voltage Controlled Oscillator (VCO), coupled to the charge pump and further coupled to the downconverter;

a divide-by-41 circuit, coupled to the VCO; and

a divide-by-7 circuit, coupled between the divide-by-41 circuit and the PFD, to make a phase locked loop.

8. The GPS RF front end of claim 7, wherein the reference oscillator can accept an external reference signal.

9. The GPS RF front end of claim 8, wherein the external reference signal is generated by a crystal.

10. The GPS RF front end of claim 9, where in the crystal generates a frequency at approximately 24.5535 MHz.

11. The GPS RF front end of claim 1, further comprising an external antenna assembly.

12. The GPS RF front end of claim 11, wherein the external antenna assembly comprises an antenna, a LNA, and an RF bandpass filter.

13. The GPS RF front end of claim 1, wherein the GPS RF front end further comprises an external loop filter.

14. The GPS RF front end of claim 1, wherein the frequency synthesizer section generates a frequency of approximately twice that of 24.5535 MHz.

15. The GPS RF front end of claim 1, wherein at least a portion of the RFIC can be powered off as determined by a signal from within the GPS RE front end.