Active-matrix driving device, electrostatic capacitance detection device, and electronic equipment
First Claim
1. A driving device comprising:
- a clocked NAND including a first reset signal input transistor, a second reset signal input transistor, and a first clocked inverter, a first electrode of the first reset signal input transistor being electrically connected to a voltage VDD, a second electrode of the first reset signal input transistor being electrically connected to an output terminal of the clocked NAND;
a clock line CLKBX line configured to provide a clock signal CLKBX to the first clocked inverter;
a clock line CLKX configured to provide a clock signal CLKX signal to the first clocked inverter; and
a reset line RST configured to provide a reset signal RST to a gate electrode of the first reset signal input transistor and a gate electrode of the second reset signal input transistor, the first reset signal input transistor being active when the reset signal RST is at low level, the second reset signal input transistor being non-active when the reset signal RST is at low level, and an output voltage from the output terminal of the clocked NAND being at high level when the reset signal RST is at low level.
2 Assignments
0 Petitions
Accused Products
Abstract
Aspects of the invention are intended to stabilize the initial state of an active matrix so as to reduce unnecessary power consumption and stabilize the operation. The driving device can include a selection device that is coupled to any of a plurality of row direction lines and any of a plurality of column direction lines, and by which a selected state and a non-selected state of the row direction lines or the column direction lines are switched to each other. The driving device can also include a device that switches to the non-selected state that switches the selection device coupled to the row direction lines or the selection device coupled to the column direction lines to a non-selected state. Selection by the selection device can be implemented after the selection device is switched to a non-selected state by the device that switches to the non-selected state.
10 Citations
11 Claims
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1. A driving device comprising:
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a clocked NAND including a first reset signal input transistor, a second reset signal input transistor, and a first clocked inverter, a first electrode of the first reset signal input transistor being electrically connected to a voltage VDD, a second electrode of the first reset signal input transistor being electrically connected to an output terminal of the clocked NAND; a clock line CLKBX line configured to provide a clock signal CLKBX to the first clocked inverter; a clock line CLKX configured to provide a clock signal CLKX signal to the first clocked inverter; and a reset line RST configured to provide a reset signal RST to a gate electrode of the first reset signal input transistor and a gate electrode of the second reset signal input transistor, the first reset signal input transistor being active when the reset signal RST is at low level, the second reset signal input transistor being non-active when the reset signal RST is at low level, and an output voltage from the output terminal of the clocked NAND being at high level when the reset signal RST is at low level. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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Specification
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- Resources
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Current Assignee138 East LCD Advancements Limited (Vector Capital Corporation)
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Original AssigneeSeiko Epson Corporation (Seiko Group)
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InventorsHara, Hiroyuki
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Primary Examiner(s)Nguyen; Chanh D.
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Assistant Examiner(s)Karimi; Pegeman
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Application NumberUS10/916,620Publication NumberTime in Patent Office1,377 DaysField of Search345/55, 345/87, 345/98, 345/100, 345/103, 345/211, 382/124US Class Current345/98CPC Class CodesG06V 40/1306 non-optical, e.g. ultrasoni...G11C 11/22 using ferroelectric elements
