Methods and systems for down-converting a signal using a complementary transistor structure

• US 7,376,410 B2
• Filed: 02/16/2006
• Issued: 05/20/2008
• Est. Priority Date: 10/21/1998
• Status: Expired due to Fees

• Current Assignee: ParkerVision, Inc.
• Original Assignee: ParkerVision, Inc.
• Inventors: Cook, Robert W., Bultman, Michael J., Sorrells, David F., Moses, Charley D. Jr., Looke, Richard C.
• Primary Examiner(s): Tran; CongVan
• Application Number:
  US11/355,167
• Publication Number:
  US 20060141975A1
• Time in Patent Office: 824 Days
• Field of Search: 455/312, 455/313, 455/315, 455/316, 455/323, 455/333, 455/311, 455/189.1, 455/130, 455/318, 455/319, 455/334
• US Class Current: 455/319
• CPC Class Codes: H03C 1/62 Modulators in which amplitude of carrier component in output is dependent upon strength of modulating signal, e.g. no carrier output when no modulating signal is present H03C1/28 - H03C1/34, H03C1/46, H03C1/48 take precedence
• CPC Class Codes: H03D 7/00 Transference of modulation from one carrier to another, e.g. frequency-changing H03D9/00, H03D11/00 take precedence; dielectric amplifiers, magnetic amplifiers, parametric amplifiers used as a frequency-changers H03F
• CPC Class Codes: H03D 7/1441 using field-effect transistors H03D7/145 takes precedence
• CPC Class Codes: H03D 7/1475 Subharmonic mixer arrangements
• CPC Class Codes: H04B 1/0025 using a sampling rate lower than twice the highest frequency component of the sampled signal for demodulation of angle-modulated signals H03D3/006
• CPC Class Codes: H04B 1/16 Circuits
• CPC Class Codes: H04B 1/28 the receiver comprising at least one semiconductor device having three or more electrodes
• CPC Class Codes: H04B 7/12 Frequency diversity
• CPC Class Codes: H04L 25/08 Modifications for reducing interference; Modifications for reducing effects due to line faults ; Receiver end arrangements for detecting or overcoming line faults
• CPC Class Codes: H04L 27/00 Modulated-carrier systems
• CPC Class Codes: H04L 27/06 Demodulator circuits; Receiver circuits
• CPC Class Codes: H04L 27/12 Modulator circuits; Transmitter circuits
• CPC Class Codes: H04L 27/14 Demodulator circuits; Receiver circuits
• CPC Class Codes: H04L 27/148 using filters, including PLL-type filters
• CPC Class Codes: H04L 27/156 with demodulation using temporal properties of the received signal, e.g. detecting pulse width
• CPC Class Codes: H04L 27/2672 Frequency domain
• CPC Class Codes: H04L 27/3881 using sampling and digital processing, not including digital systems which imitate heterodyne or homodyne demodulation

Abstract

Methods, systems, and apparatuses for down-converting an electromagnetic (EM) signal by aliasing the EM signal are described herein. Briefly stated, such methods, systems, and apparatuses operate by receiving an EM signal and an aliasing signal having an aliasing rate. The EM signal is aliased according to the aliasing signal to down-convert the EM signal. The term aliasing, as used herein, refers to both down-converting an EM signal by under-sampling the EM signal at an aliasing rate, and down-converting an EM signal by transferring energy from the EM signal at the aliasing rate. In an embodiment, the EM signal is down-converted to an intermediate frequency (IF) signal. In another embodiment, the EM signal is down-converted to a demodulated baseband information signal. In another embodiment, the EM signal is a frequency modulated (FM) signal, which is down-converted to a non-FM signal, such as a phase modulated (PM) signal or an amplitude modulated (AM) signal.

Claims

1. A circuit that down-converts a first signal to produce a lower frequency second signal, comprising:

a pulse generator to generate a control signal including a plurality of pulses, each pulse of the plurality of pulses having an aperture; and

an energy transfer module to sub-sample the first signal to transfer energy therefrom;

wherein the energy transfer module includes a complementary transistor structure and is controlled by the control signal.

2. The circuit of claim 1, wherein the complementary transistor structure is a complementary field effect transistor (FET) structure.

3. The circuit of claim 1, wherein respective apertures of the plurality of pulses are approximately one-half of a period of the first signal.

4. The circuit of claim 1, wherein respective apertures t_p of the plurality of pulses are related to a period T of the first signal according to the equation t_p=Y*T, and wherein Y is a fraction.

5. The circuit of claim 1, wherein respective apertures t_p of the plurality of pulses are related to a period T of the first signal according to the equation t_p=(N+Y)*T, and wherein N is an integer and Y is a fraction.

6. The circuit of claim 1, wherein the energy transfer module substantially distorts the first signal.

7. The circuit of claim 1, further comprising:

a delay coupled between the pulse generator and a first transistor of the complementary transistor structure; and

an inverter coupled between the pulse generator and a second transistor of the complementary transistor structure.

8. The circuit of claim 7, wherein a time delay associated with the delay and a time delay associated with the inverter are substantially same.

9. The circuit of claim 7, wherein the first and second transistors have a common first node to receive the first signal and a common second node to provide the energy, wherein the first transistor has a first control node coupled to the delay, and wherein the second transistor has a second control node coupled to the inverter.

10. The circuit of claim 1, further comprising:

a storage module to store the energy received from the energy transfer module;

wherein the lower frequency second signal is based on the energy.

11. A method of down-converting a first signal to produce a lower frequency second signal, comprising:

generating a control signal including a plurality of pulses, each pulse of the plurality of pulses having an aperture; and

sub-sampling the first signal to transfer energy therefrom using a complementary transistor structure controlled by the control signal.

12. The method of claim 11, wherein sub-sampling the first signal includes sub-sampling the first signal to transfer energy therefrom using a complementary field effect transistor (FET) structure controlled by the control signal.

13. The method of claim 11, wherein respective apertures of the plurality of pulses are approximately one-half of a period of the first signal.

14. The method of claim 11, wherein respective apertures t_p of the plurality of pulses are related to a period T of the first signal according to the equation t_p=Y*T, and wherein Y is a fraction.

15. The method of claim 11, wherein respective apertures t_p of the plurality of pulses are related to a period T of the first signal according to the equation t_p=(N+Y)*T, and wherein N is an integer and Y is a fraction.

16. The method of claim 11, further comprising:

substantially distorting the first signal in response to sub-sampling the first signal.

17. The method of claim 11, further comprising:

delaying the control signal to provide a delayed control signal;

inverting the control signal to provide an inverted control signal;

controlling a first transistor of the complementary transistor structure using the delayed control signal, and

controlling a second transistor of the complementary transistor structure using the inverted control signal.

18. The circuit of claim 17, wherein delaying the control signal includes delaying the control signal for a first amount of time, wherein inverting the control signal includes delaying the control signal for a second amount of time, and wherein the first and second amounts of time are substantially same.

19. The method of claim 11, further comprising:

storing the energy to produce the lower frequency second signal.

20. A method of down-converting a first signal to produce a lower frequency second signal, comprising:

sub-sampling the first signal to transfer energy therefrom using a complementary transistor structure; and

controlling the complementary transistor structure to perform the sub-sampling using pulses of a control signal, each pulse of the control signal having an aperture.

21. The method of claim 20, wherein sub-sampling the first signal includes sub-sampling the first signal to transfer energy therefrom using a complementary field effect transistor (FET) structure.

22. The method of claim 20, wherein respective apertures of the plurality of pulses are approximately one-half of a period of the first signal.

23. The method of claim 20, wherein respective apertures t_p of the plurality of pulses are related to a period T of the first signal according to the equation t_p=Y*T, and wherein Y is a fraction.

24. The method of claim 20, wherein respective apertures t_p of the plurality of pulses are related to a period T of the first signal according to the equation t_p=(N+Y)*T, and wherein N is an integer and Y is a fraction.

25. The method of claim 20, further comprising:

substantially distorting the first signal in response to sub-sampling the first signal.

26. The method of claim 20, further comprising:

delaying the control signal to provide a delayed signal; and

inverting the control signal to provide an inverted signal;

wherein controlling the complementary transistor structure includes

controlling a first transistor of the complementary transistor structure using the delayed signal, and

controlling a second transistor of the complementary transistor structure using the inverted signal.

27. The circuit of claim 26, wherein delaying the control signal includes delaying the control signal for a first amount of time, wherein inverting the control signal includes delaying the control signal for a second amount of time, and wherein the first and second amounts of time are substantially same.

28. The method of claim 20, further comprising:

storing the energy to produce the lower frequency second signal.