TCP/IP processor and engine using RDMA

• US 7,376,755 B2
• Filed: 06/10/2003
• Issued: 05/20/2008
• Est. Priority Date: 06/11/2002
• Status: Active Grant

• Current Assignee: Memory Access Technologies LLC
• Original Assignee: Ashish A. Pandya
• Inventors: Pandya, Ashish A.
• Primary Examiner(s): Etienne, Ario
• Assistant Examiner(s): Halim, Sahera
• Application Number:
  US10/459,349
• Publication Number:
  US 20040037319A1
• Time in Patent Office: 1,806 Days
• Field of Search: 709/250, 709/212, 370/386, 370/388, 711/5, 707/1
• US Class Current: 709/250
• CPC Class Codes: H04L 67/1097 for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS]
• CPC Class Codes: H04L 67/34 involving the movement of software or configuration parameters network booting or remote initial program loading [RIPL] G06F9/4416
• CPC Class Codes: H04L 69/10 Streamlined, light-weight or high-speed protocols, e.g. express transfer protocol [XTP] or byte stream
• CPC Class Codes: H04L 69/12 Protocol engines
• CPC Class Codes: H04L 69/16 Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
• CPC Class Codes: H04L 69/161 Implementation details of TCP/IP or UDP/IP stack architecture; Specification of modified or new header fields
• CPC Class Codes: H04L 69/163 In-band adaptation of TCP data exchange; In-band control procedures
• CPC Class Codes: H04L 69/165 Combined use of TCP and UDP protocols; selection criteria therefor
• CPC Class Codes: H04L 69/166 IP fragmentation; TCP segmentation
• CPC Class Codes: H04L 69/18 Multiprotocol handlers, e.g. single devices capable of handling multiple protocols
• CPC Class Codes: H04L 69/32 Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
• CPC Class Codes: H04L 69/323 in the physical layer [OSI layer 1]
• CPC Class Codes: H04L 69/326 in the transport layer [OSI layer 4] H04L69/16 takes precedence
• CPC Class Codes: H04L 69/329 in the application layer [OSI layer 7]
• CPC Class Codes: H04L 9/40 Network security protocols

Abstract

A TCP/IP processor and data processing engines for use in the TCP/IP processor is disclosed. The TCP/IP processor can transport data payloads of Internet Protocol (IP) data packets using an architecture that provides capabilities to transport and process Internet Protocol (IP) packets from Layer 2 through transport protocol layer and may also provide packet inspection through Layer 7. The engines may perform pass-through packet classification, policy processing and/or security processing enabling packet streaming through the architecture at nearly the full line rate. A scheduler schedules packets to packet processors for processing. An internal memory or local session database cache stores a TCP/IP session information database and may also store a storage information session database for a certain number of active sessions. The session information that is not in the internal memory is stored and retrieved to/from an additional memory. An application running on an initiator or target can in certain instantiations register a region of memory, which is made available to its peer(s) for access directly without substantial host intervention through RDMA data transfer.

Claims

1. A programmable TCP/IP processor engine, said processor having RDMA capability and used for processing Internet Protocol packets, said TCP/IP processor engine comprising:

a checksum component for TCP/IP checksum verification and for new checksum generation;

a data memory for storing said packets;

an execution resource;

a packet look-up interface for assisting an execution resource and an instruction sequencer for providing access to said data packets or predetermined data packet fields thereof;

an instruction decoder to direct said TCP/IP processor engine operation based on the results of a classification processor;

a sequence and window operation manager providing specific segmenting, sequencing and windowing operations for use in TCP/IP data sequencing calculations;

and further comprising;

a hash engine used to perform hash operations against predetermined fields of the packet to perform a hash table walk to determine the correct session entry for said packet;

a register file for extracting predetermined header fields from said packets for TCP processing;

pointer registers for indicating data source and destination;

context register sets for holding multiple contexts for packet execution;

said multiple contexts allowing, in response to a given packet execution stalling, another context to be invoked to enable said TCP/IP processor engine to continue the execution of another packet stream;

 

said TCP/IP processor engine having a cache for holding recently or frequently used session entries, including connection IDs, for local use;

 

and further having an interface for informing a packet scheduler of the connection IDs that are cached for each TCP/IP processor engine resource.

2. The TCP/IP processor engine of claim 1 further comprising a session database lookup engine and a session manager which, in response to an indication that the packet processor does not hold the session entry for the specific connection required for said session, work with said hash engine to retrieve said session entry from a global session memory through a memory controller interface and to replace said session entry in said packet processor.

3. The combination of claim 2 wherein the session manager includes means, operative upon fetching of a session entry or its fields corresponding to a packet being processed by said TCP/IP processor engine, said means working with said hash engine to generate a session identifier for retrieving the corresponding session entry or its fields from a session database cache.

4. The combination of claim 2 wherein the session manager includes means, operative upon storing of a session entry or its fields corresponding to the packet being processed by said TCP/IP processor engine, said means acting with the said hash engine to generate a session identifier, for storing the corresponding session entry or its fields to the session database cache to replace a session entry as a result of packet processing.

5. The session database look-up engine of claim 2 further comprising means operative upon the fetching of a new session entry from said global session memory, said means storing the replaced session entry in said global session memory.

6. The TCP/IP processor engine of claim 2 wherein said session entry in said cache is exclusively cached to one of a plurality of processors so that request for access to said cache by more than one of said plurality does not cause any race conditions by non-exclusive access.

7. The TCP/IP processor engine of claim 6 wherein when a session entry is exclusively cached to one processor, and another processor requests said session entry, said entry is transferred to the requesting processor with exclusive access to said session entry.

8. The TCP/IP processor engine of claim 2 further comprising a programmable frame controller and out of order manager used for extracting frame information from said packets and performing operations for execution of packets received out of order from the expected sequence for their session or flow.

9. The TCP/IP processor engine of claim 8 operating on an upper layer and having an upper layer framing mechanism used by said programmable frame controller and out of order manager to extract the embedded PDUs from packets arriving out of order and allowing said PDUs to be directed to an end buffer destination.

10. The TCP/IP processor engine of claim 9 wherein said programmable frame controller operates on retransmitted packets.

11. The combination of claim 9 wherein the frame controller and out of order manager includes a cyclic redundancy check generator for identifying, verifying and delineating markers in the upper layer frames from the received network packets or generating the upper layer frame markers using CRC codes for packets directed to the network.

12. The TCP/IP processor engine of claim 1 further comprising a TCP state machine capable of state transitions and capable of having a current state and generating a next state, said state machine receiving

a state information stored in the session entry;

and

appropriate fields affecting said state information from a fetched or newly received packet being processed for allowing the state machine to generate said next state if there is a state transition, and updating information in said session entry in cache to indicate said next state.

13. The TCP/IP processor engine of claim 1 including a storage engine queue which, if a packet belongs to a storage data transfer, receives one of said packets having a storage payload, or the storage payload of said packet, for processing by a storage engine.

14. The TCP/IP processor engine of claim 1 including a segmentation controller for segmenting data to be sent on the IP Network to create valid packets to transport said segmented data on the IP network.

15. The TCP/IP processor engine of claim 1 including a DMA engine for retrieving packets or commands or combinations thereof from a scheduler or a host, and storing said packets or commands or data to internal memory of a packet processor for further processing by the packet processor.

16. The TCP/IP processor engine of claim 15 including a processor for processing the said packets having packet data and extracting the packet data for transfer to an end buffer destination in a host processor.

17. The TCP/IP processor engine of claim 15 including at least one processor for processing the said host commands or retrieving outgoing host data or a combination of any of the foregoing using the said DMA engine, for additional processing by the TCP/IP processor engine to form an outgoing packet for transfer onto the IP network.

18. The TCP/IP processor engine of claim 1 further comprising means in a packet processor engine for additional processing of said packet by execution of additional processing application code.

19. The TCP/IP processor engine of claim 18 wherein said additional processing application code can be executed on said packet before or after processing by the TCP/IP, processor engine or an IP Storage processor engine or a combination thereof.

20. The TCP/IP processor engine of claim 1 wherein said session entry in cache is cached using the Modified Exclusive Shared Invalid algorithm.